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Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout

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Abstract

In this paper the power consumption and power integrity of a CMOS ring oscillator has been analysed when their pFETs are subjected to negative bias temperature instability (NBTI). The impact of pFET under NBTI has been experimentally quantified whereas CMOS ring oscillator power consumption and power integrity have been evaluated by means of electrical full-model simulation. The results show that power consumption is reduced and power integrity remains constant with NBTI wearout..

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Acknowledgments

This work has been partially supported by Generalitat de Catalunya (SGR2009-1425) and the Spanish Government (TEC2010-18550).

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Authors and Affiliations

  1. Escuela Universitaria Salesiana de Sarriá, Psg. Sant Joan Bosco 74, Barcelona, 08017, Spain

    J. M. Ruiz & M. Morata

  2. Department of Electronics Engineering, UPC Barcelona Tech, Colom 1, Terrassa, 08222, Spain

    R. Fernández-Garcia & I. Gil

Authors
  1. J. M. Ruiz
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  2. R. Fernández-Garcia
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  3. I. Gil
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  4. M. Morata
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Correspondence to J. M. Ruiz.

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Responsible Editor: K. K. Saluja

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Ruiz, J.M., Fernández-Garcia, R., Gil, I. et al. Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout. J Electron Test 28, 865–868 (2012). https://doi.org/10.1007/s10836-012-5337-9

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  • DOI: https://doi.org/10.1007/s10836-012-5337-9

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