Skip to main content
SpringerLink
Log in

Eliminating the Timing Penalty of Scan

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a pair of scan cell transformation techniques that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. The first technique is an ad-hoc technique, while the second one is the retiming technique applied on the scan logic. The proposed transformation techniques retain the test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan in a cost-effective way and thus enhancing the functional speed of integrated circuits.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

Notes

  1. The two signals Test and Scan_en are typically available from the input pins or are generated by the test access port (TAP) controller. During the test mode, the Test signal is always high, while it is low during the normal mode; the Scan_en signal is high during the shift mode, and low during the capture mode.

  2. A single dummy clock pulse may be required prior to all the clock pulses in order to set the Sel_shadow (or EN_del) signal to 1; both Scan_en and Sel_shadow (or EN_del) signals are high throughout scan chain testing.

  3. The pattern to be loaded into the untransformed scan cells and shadow flip-flops is the two patterns merged together: the pattern for stuck-at-v fault on the original flip-flop input and the pattern for the transition fault (from \(v'\) to v) at the output of the original flip-flop. This way, the pre-capture pulse justifies the original flip-flop to \(v'\) prior to double capture.

References

  1. Abramovici M, Kulikowski JJ, Roy RK (1991) The best flip-flops to scan. In: Proc. international test conference, pp 166–173

  2. Agrawal VD, Cheng K-T, Johnson DD, Lin ST (1988) Designing circuits with partial scan. IEEE Des Test Comput 5(2):8–15

    Article  Google Scholar 

  3. Ashar P, Malik S (1994) Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications. In: Proc. design automation conference, pp 77–80

  4. Boppana V, Fuchs WK (1996) Partial scan design based on state transition modeling. In: Proc. international test conference, pp 538–547

  5. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory & mixed-signal vlsi circuits. Springer

  6. Chakradhar ST, Balakrishnan A, Agrawal VD (1994) An exact algorithm for selecting partial scan flip-flops. In: Proc. 31st design automation conference, pp 81–86

  7. Chakradhar ST, Dey S (1994) Resynthesis and retiming for optimum partal scan. In: Proc. 31st design automation conf, pp 87–93

  8. Cheng K-T (1995) Single clock partial scan. IEEE Des Test Comput 12(2):24–31

    Article  Google Scholar 

  9. Cheng K-T, Agrawal VD (1990) A partial scan method for sequential circuits with feedback. IEEE Trans Comput 39(4):544–548

    Article  Google Scholar 

  10. Chickermane V, Patel JH (1990) An optimization based approach to the partial scan design problem. In: Proc. international test conference, pp 377–386

  11. Chickermane V, Patel JH (1991) A fault oriented partial scan design approach. In: Proc. international conference on computer-aided design, pp 400–403

  12. De Micheli G (1994) Synthesis and optimization of digital circuits. McGraw-Hill, New York

    Google Scholar 

  13. Gupta RM, Breuer A (1990) The ballast methodology for structured partial scan design. IEEE Trans Comput 39(4):538–544

    Article  Google Scholar 

  14. Hardware implementations of ecrypt stream ciphers (2012) VHDL code available from http://eeweb.poly.edu/faculty/karri/stream_ciphers/index.html. Accessed 15 Feb 2012

  15. Higami Y, Kajihara S, Kinoshita K (1995) Test sequence compaction by reduced scan shift and retiming. In: Proc. 4th Asian test symp, pp 169–175

  16. Hsiao MS, Saund GS, Rudnick EM, Patel JH (1998) Partial scan selection based on dynamic reachability and observability information. In: Proc. international conference on VLSI design, pp 174–180

  17. Jou J-Y, Cheng K-T (1991) Timing-driven partial scan. In: Proc. international conference on computer-aided design, pp 404–407

  18. Kagaris D, Tragoudas S (1996) Retiming-based partial scan. IEEE Trans Comput 45(1):74–87

    Article  MATH  Google Scholar 

  19. Kalla P, Ciesielski M (2002) A comprehensive approach to the partial scan problem using implicit state enumeration. IEEE Trans Comput Aided Des Integr Circ Syst 21(7):810–826

    Article  Google Scholar 

  20. Khan O, Bushnell ML, Devanathan SK, Agrawal VD (2007) SPARTAN: A spectral and information theoretic approach to partial scan. In: Proc. international test conference. Paper 21.1

  21. Kim KS, Kime CR (1990) Partial scan by use of empirical testability. In: Proc. international conference on computer-aided design, pp 314–317

  22. Kunzmann A, Wunderlich HJ (1990) An analytical approach to the partial scan design problem. J Electron Test Theory Appl 1:163–174

    Article  Google Scholar 

  23. Lee DH, Reddy SM (1990) On determining scan flip-flops in partial-scan designs. In: Proc. international conference on computer-aided design, pp 322–325

  24. Leiserson CE, Rose F, Saxe JB (1983) Optimizing synchronous circuits by retiming. In: Proc. 3rd caltech conf. on VLSI, pp 87–116

  25. Leiserson CE, Saxe JB (1991) Retiming synchronous circuitry. Algorithmica 6:5–35

    Article  MathSciNet  MATH  Google Scholar 

  26. Liang H-C, Lee CL (1999) An effective methodology for mixed scan and reset design based on test generation and structure of sequential circuits. In: Proc. 8th Asian test symposium, pp 173–178

  27. Lin X, Pomeranz I, Reddy SM (1999) Full scan fault coverage with partial scan. In: Proc. design automation and test in Europe, pp 468–472

  28. Maheshwari N, Sapatnekar SS (1999) Timing analysis and optimization of sequential circuits. Springer

  29. Parikh PS, Abramovici M (1995) Testability-based partial scan analysis. J Electron Test Theory Appl 7:47–60

    Article  Google Scholar 

  30. Park I, Ha DS, Sim G (1995) A new method for partial scan design based on propagation and justification requirements of faults, pp 413–422

  31. Park J, Shin S, Park S (2000) A partial scan design by unifying structural analysis and testabilities. In: Proc. international symposium on circuits and systems, vol 1, pp 88–91

  32. Saund GS, Hsiao MS, Patel JH (1997) Partial scan beyond cycle cutting. In: Proc. international symposium on fault-tolerant computing, pp 320–328

  33. Sharma S, Hsiao MS (2001) Combination of structural and state analysis for partial scan. In: Proc. international conference on VLSI design, pp 134–139

  34. Sinanoglu O (2012) Eliminating performance penalty of scan. In: Proc. 25th international conf VLSI design, pp 346–351

  35. Sinanoglu O, Agrawal VD (2012) Retiming scan circuit to eliminate timing penalty. In: Proc. 13th Latin American test workshop, pp 137–142

  36. Tai S-E, Bhattacharya D (1994) A three-stage partial scan design method using the sequential circuit flow graph. In: Proc. international conference on VLSI design, pp 101–106

  37. Trischler E (1980) Incomplete scan path with an automatic test generation methodology. In: Proc. international test conference, pp 153–162

  38. Xiang D, Patel JH (1996) A global algorithm for the partial scan design problem using circuit state information. In: Proc. international test conference, pp 548–557

  39. Xiang D, Patel JH (2004) Partial scan design based on circuit state information and functional analysis. IEEE Trans Comput 53(3):276–287

    Article  Google Scholar 

  40. Xiang D, Venkataraman S, Fuchs WK, Patel JH (1996) Partial scan design based on circuit state information. In: Proc. design automation conference, pp 807–812

Download references

Author information

Authors and Affiliations

  1. Department of Computer Engineering, New York University Abu Dhabi, PO Box 129188, Abu Dhabi, UAE

    Ozgur Sinanoglu

  2. Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, 36849, USA

    Vishwani D. Agrawal

Authors
  1. Ozgur Sinanoglu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Vishwani D. Agrawal
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ozgur Sinanoglu.

Additional information

Responsible Editor: L. M. Bolzani Pöhls

Rights and permissions

Reprints and permissions

About this article

Cite this article

Sinanoglu, O., Agrawal, V.D. Eliminating the Timing Penalty of Scan. J Electron Test 29, 103–114 (2013). https://doi.org/10.1007/s10836-013-5352-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-013-5352-5

Keywords

Search

Navigation