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A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic

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Abstract

Input vector monitoring concurrent on-line BIST based on multilevel decoding logic is an attractive approach to reduce hardware overhead. In this paper, a novel optimization scheme is proposed for further reducing the hardware overhead of the decoding structure, which refers to improved decoding, input reduction, and simulated annealing inputs swapping approaches. Furthermore, utilizing similar multilevel decoding logic as the responses verifier, a novel cost-efficient input vector monitoring concurrent on-line BIST scheme is presented. The proposed scheme is applicable to the concurrent on-line testing for the CUT, the detail of which can not be obtained, such as hard IP cores. Experimental results indicate that the proposed optimization approaches can significantly reduce the hardware overhead of the decoding structure, and the proposed scheme costs lower hardware than other existing schemes.

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Acknowledgments

This work is supported by Hunan Provincial Innovation Foundation For Postgraduate (No. CX2012B031).

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Authors and Affiliations

  1. School of Computer Science, National University of Defense Technology, Changsha, China

    Tie-Bin Wu, Heng-Zhu Liu, Peng-Xia Liu, Dong-Sheng Guo & Hai-Ming Sun

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  1. Tie-Bin Wu
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  2. Heng-Zhu Liu
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  3. Peng-Xia Liu
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  4. Dong-Sheng Guo
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  5. Hai-Ming Sun
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Correspondence to Tie-Bin Wu.

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Responsible Editor: H. J. Wunderlich

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Wu, TB., Liu, HZ., Liu, PX. et al. A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic. J Electron Test 29, 585–600 (2013). https://doi.org/10.1007/s10836-013-5380-1

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  • DOI: https://doi.org/10.1007/s10836-013-5380-1

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