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Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

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Abstract

We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures.

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References

  1. Alaghi A, Karimi N, Sedghi M, Navabi Z (2007) Online NoC switch fault detection and diagnosis using a high level fault model. In: 22nd IEEE International symposium on defect and fault-tolerance in VLSI systems, 2007. DFT ’07, pp 21–29

  2. Balfour J, Dally WJ (2006) Design tradeoffs for tiled cmp on-chip networks. In: Proceedings of the 20th annual international conference on supercomputing (ICS), pp 187–198

  3. Banerjee N, Vellanki P, Chatha KS (2004) A power and performance model for network-on-chip architectures. In: Proceedings of design, automation and test in Europe conference and exhibition, 2004, vol 2. pp 1250–1255

  4. Chen X, Peh L-S (2003) Leakage power modeling and optimization in interconnection networks. In: Proceedings of the 2003 international symposium on low power electronics and design, 2003. ISLPED ’03, pp 90–95

  5. Concatto C, Matos D, Carro L, Kastensmidt F, Susin A, Cota E, Kreutz M (2009) Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router. In: Proceedings of the 22nd annual symposium on integrated circuits and system design: chip on the Dunes, SBCCI ’09. ACM, pp 26:1–6

  6. Constantinescu C (2003) Trends and challenges in vlsi circuit reliability, vol 23. pp 14–19

  7. De Micheli G, Benini L (2006) Networks On Chips: technology and tools. Morgan Kaufmann Publishers, San Mateo

    Google Scholar 

  8. Dumitras T, Marculescu R (2003) On-chip stochastic communication [soc applications]. In: Design, automation and test in Europe conference and exhibition, 2003, pp 790–795

  9. Fick D, DeOrio A, Chen G, Bertacco V, Sylvester D, Blaauw D (2009) A highly resilient routing algorithm for fault-tolerant NoCs. In: Design, automation test in Europe conference exhibition, 2009. DATE ’09, pp 21–26, 20–24

  10. Fick D, DeOrio A, Jin H, Bertacco V, Blaauw D, Sylvester D (2009) Vicis: a reliable network for unreliable silicon. In: Proceedings of the 46th annual design automation conference, DAC ’09. ACM, pp 812–817

  11. Frantz AP, Kastensmidt FL, Carro L, Cota E (2006) Dependable network-on-chip router able to simultaneously tolerate soft errors and crosstalk. In: IEEE international test conference, 2006. ITC ’06. pp 1–9

  12. Grecu C, Ivanov A, Saleh R, Sogomonyan ES, Pande PP (2006) On-line fault detection and location for noc interconnects. In: 12th IEEE international on-line testing symposium, 2006. IOLTS 2006, p 6

  13. Guindani G, Reinbrecht C, Raupp T, Calazans N, Moraes FG (2008) NoC power estimation at the rtl abstraction level. In: Symposium on VLSI, 2008. ISVLSI ’08. IEEE Computer Society Annual, pp 475–478

  14. Kim D, Lee K, Se JL, Yoo H-J (2005) A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. In: IEEE international symposium on circuits and systems, 2005, vol 3. ISCAS 2005, pp 2369–2372

  15. Koibuchi M, et al. (2008) A lightweight fault-tolerant mechanism for Network-on-Chip. In: International symposium on Networks-on-Chip (NoCS), pp 13–22

  16. Lan Y-C, Lo S-H, Lin Y-C, Hu Y-H, Chen S-J (2009) BiNoC: a bidirectional NoC architecture with dynamic self-reconfigurable channel. In: 3rd ACM/IEEE international symposium on Networks-on-Chip, 2009. NoCS 2009, pp 266–275

  17. Latif K, Rahmani AM, Vaddina KR, Seceleanu T, Liljeberg P, Tenhunen H (2011) Enhancing performance of noc-based architectures using heuristic virtual-channel sharing approach. In: 35th IEEE annual computer software and applications conference (COMPSAC), pp 442–447

  18. Lehtonen T (2009) On fault tolerance methods for networks-on-chip. Ph.D. Thesis, University of Turku, Finland

  19. Lehtonen T, Liljeberg P, Plosila J (2007) Fault tolerance analysis of NoC architectures. In: IEEE international symposium on circuits and systems, 2007. ISCAS 2007, pp 361–364

  20. Li F, Nicopoulos C, Richardson T, Xie Y, Narayanan V, Kandemir M (2006) Design and management of 3d chip multiprocessors using network-in-memory. In: 33rd international symposium on computer architecture, 2006. ISCA ’06, pp 130–141

  21. Lotfi-Kamran P, Rahmani AM, Daneshtalab M, Afzali-Kusha A, Navabi Z (2010) EDXY—a low cost congestion-aware routing algorithm for network-on-chips. J Syst Archit 56(7):256–264

    Article  Google Scholar 

  22. Mullins R, West A, Moore S (2004) Low-latency virtual-channel routers for on-chip networks. In: 31st annual international symposium on computer architecture, Proceedings, pp 188–197

  23. Murali S, Seiculescu C, Benini L, De Micheli G (2009) Synthesis of networks on chips for 3d systems on chips. In: Asia and South Pacific design automation conference, 2009. ASP-DAC 2009, pp 242–247

  24. Neishaburi MH, Zilic Z (2009) Reliability aware NoC router architecture using input channel buffer sharing. In: ACM Great Lakes symposium on VLSI, pp 511–516

  25. Neishaburi MH, Zilic Z (2011) ERAVC: enhanced reliability aware NoC router. In: 12th international symposium on quality electronic design (ISQED), pp 1–6

  26. Ni LM, McKinley PK (1993) A survey of wormhole routing techniques in direct networks. Computer 26(2):62–76

    Article  Google Scholar 

  27. Nicopoulos CA et al (2006) Vichar: a dynamic virtual channel regulator for network-on-chip routers. In: 39th annual IEEE/ACM international symposium on microarchitecture, 2006. MICRO-39, pp 333–346

  28. Pasricha S, Dutt N (2008) On-Chip communication architectures: system on chip interconnect. Morgan Kaufmann, San Mateo

    Google Scholar 

  29. Rahmani AM, Afzali-Kusha A, Pedram M (2009) NED: a novel synthetic traffic pattern for power/performance analysis of network-on-chips using negative exponential distribution. J Low Power Electron (American Scientific Publishers) 5:396–405

    Article  Google Scholar 

  30. Rahmani A-M, Latif K, Vaddina KR, Liljeberg P, Plosila J, Tenhunen H (2011) Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures. In: Fifth IEEE/ACM international symposium on networks on chip (NoCS’11), pp 65–72

  31. Ramanujam RS, Soteriou V, Lin B, Peh L-S (2010) Design of a high-throughput distributed shared-buffer NoC router. In: NOCS ’10: Proceedings of the 2010 Fourth ACM/IEEE international symposium on networks-on-chip, pp 69–78

  32. Shen J-S, Huang C-H, Hsiung P-A (2010) Learning-based adaptation to applications and environments in a reconfigurable network-on-chip. In: Design, automation test in Europe conference exhibition (DATE), 2010, pp 381–386

  33. Rao Vaddina K, Nigussie E, Liljeberg P, Plosila J (2009) Self-timed thermal monitoring of multicore systems. In: 12th IEEE symposium on design and diagnostics of electronic circuits and systems (DDECS’09), pp 246–251

  34. Valinataj M, Mohammadi S, Plosila J, Liljeberg P, Tenhunen H (2011) A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip. AEU - Int J Electron Commun 65(7):630–640

    Article  Google Scholar 

  35. Towles BP, Dally WJ (2004) Principles and practices of interconnection networks. The Morgan Kaufmann Series in Computer Architecture and Design

  36. Yaghini PM, Eghbal A, Pedram H, Zarandi HR (2010) Investigation of transient fault effects in an asynchronous NoC router. In: 18th Euromicro international conference on parallel, distributed and network-based processing (PDP), 2010, pp 540–545

  37. Ye TT, Benini L, De Micheli G (2002) Analysis of power consumption on switch fabrics in network routers. In: Design automation conference (DAC), 2002. Proceedings. 39th, pp 524–529

  38. Zhang Z, Greiner A, Taktak S (2008) A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. In: 45th ACM/IEEE DAC conference, pp 441–446

  39. Zonouz AE, Seyrafi M, Asad A, Soryani M, Fathy M, Berangi R (2009) A fault tolerant NoC architecture for reliability improvement and latency reduction. In: 12th Euromicro conference on digital system design, architectures, methods and tools, pp 473–480

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Authors and Affiliations

  1. University of Turku and Turku Centre for Computer Science, Turku, Finland

    Khalid Latif, Amir-Mohammad Rahmani, Ethiopia Nigussie & Hannu Tenhunen

  2. ABB Corporate Research Centre and Mälardalen University, Västerås, Sweden

    Tiberiu Seceleanu

  3. University of Stuttgart, Stuttgart, Germany

    Martin Radetzki

Authors
  1. Khalid Latif
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  2. Amir-Mohammad Rahmani
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  3. Ethiopia Nigussie
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  4. Tiberiu Seceleanu
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  5. Martin Radetzki
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  6. Hannu Tenhunen
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Correspondence to Khalid Latif.

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Responsible Editor: M. Violante

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Latif, K., Rahmani, AM., Nigussie, E. et al. Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. J Electron Test 29, 431–452 (2013). https://doi.org/10.1007/s10836-013-5389-5

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  • DOI: https://doi.org/10.1007/s10836-013-5389-5

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