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A Fault Tolerant Hierarchical Network on Chip Router Architecture

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Abstract

Continuing advances in the processing technology, along with the significant decreases in the feature size of integrated circuits lead to increases in susceptibility to transient errors and permanent faults. Network on Chips (NoCs) have come to address the demands for high bandwidth communication among processing elements. The structural redundancy inherited in NoC-based design can be exploited to improve reliability and compensate for the effects of failures. In this paper, we propose an enhanced fault tolerant microarchitecture with deadlock-free routing for Hierarchical NoCs. The proposed router supplies dynamic Virtual Channel (VC) Allocation, and it employs a high-performance fault tolerant control flow, handling both transient and permanent faults in hierarchical networks without extra retransmission buffer requirements. Experimental results show a significant improvement in reliability as well as decreases in the average latency and energy consumption.

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Authors and Affiliations

  1. Department of Electrical Engineering, McGill University, Montreal, QC, Canada

    M. H. Neishaburi & Zeljko Zilic

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  1. M. H. Neishaburi
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  2. Zeljko Zilic
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Correspondence to M. H. Neishaburi.

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Responsible Editor: M. Violante

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Neishaburi, M.H., Zilic, Z. A Fault Tolerant Hierarchical Network on Chip Router Architecture. J Electron Test 29, 485–497 (2013). https://doi.org/10.1007/s10836-013-5398-4

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  • DOI: https://doi.org/10.1007/s10836-013-5398-4

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