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Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

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Abstract

Growing test data volume and excessive test application time are two serious concerns in scan-based testing for SoCs. This paper presents an efficient test-independent compression technique based on block merging and eight coding (BM-8C) to reduce the test data volume and test application time. Test compression is achieved by encoding the merged blocks after merging consecutive compatible blocks with exact eight codewords. The proposed scheme compresses the pre-computed test data without requiring any structural information of the circuit under test. Therefore, it is applicable for IP cores in SoCs. Experimental results demonstrate that the BM-8C technique can achieve an average compression ratio up to 68.14 % with significant low test application time.

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Acknowledgment

This work is supported by Hunan Provincial Innovation Foundation For Postgraduate (no. CX2012B031). The authors would like to thank Dr. A. H. El-Maleh from King Fahd University of Petroleum and Minerals, Dr. Yinhe Han and Jun Liu from Chinese Academy of Sciences for providing test sets used in this paper.

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Authors and Affiliations

  1. School of Computer Science, National University of Defense Technology, Changsha, China

    Tie-Bin Wu, Heng-Zhu Liu & Peng-Xia Liu

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  1. Tie-Bin Wu
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  2. Heng-Zhu Liu
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  3. Peng-Xia Liu
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Correspondence to Tie-Bin Wu.

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Responsible Editor: N. A. Touba

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Wu, TB., Liu, HZ. & Liu, PX. Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding. J Electron Test 29, 849–859 (2013). https://doi.org/10.1007/s10836-013-5415-7

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  • DOI: https://doi.org/10.1007/s10836-013-5415-7

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