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A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs

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Abstract

Three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC (2D IC), including heterogeneous integration, reduced delay and power dissipation, compact device dimension, etc. Wafer-on-wafer stacking offers practical advantages in 3D IC fabrication, but it suffers from low compound yield. To improve the yield, a novel manipulation scheme of wafer named n-sector symmetry and cut (SSCn) is proposed. In this method, wafers with rotational symmetry are cut into n identical sectors, where n is a suitably chosen integer. The sectors are then used to replenish repositories. The SSCn method is combined with best-pair matching algorithm for compound yield evaluation. Simulation of wafers with nine different defect distributions shows that previously known plain rotation of wafers offers only a trivial benefits in yield. A cut number four is optimal for most of the defect models. The SSC4 provides significantly higher yield and the advantage becomes more obvious with increase of the repository size and the number of stacked layers. Cost model of SSCn is analyzed and the cost-effectiveness of SSC4 is established. Observations made are: 1) Cost benefits of SSC4 become larger as the manufacturing overhead of SSC4 become smaller, 2) cost improvement of SSC4 over conventional basic method increases as the number of stacked layers increases and 3) for most defect models, SSC4 largely reduces the cost even when manufacturing overhead of SSC4 is considered to be very large.

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Acknowledgments

This research is supported in part by the National Science Foundation Grant CCF-1116213. The authors would like to thank Jiao Yu for her useful comments.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, 36849, USA

    Bei Zhang & Vishwani D. Agrawal

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  1. Bei Zhang
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  2. Vishwani D. Agrawal
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Correspondence to Bei Zhang.

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Responsible Editor: T. Xia

This research was originally presented at the Twenty-second IEEE North Atlantic Test Workshop, May 2013.

Appendix

Appendix

Figure 16 shows the final production size of good 3D ICs considering different number of cuts. Same setup as in Section 5.1 applies here. As we can see, in most cases four-cuts produces the largest number of good 3D ICs. Note that 2 cuts are not used in these experiments because DPW of 2 cuts is identical to that for 4 cuts. However, 2-cuts provide less flexibility in matching and will definitely yield fewer good 3D ICs than 4 cuts. Also note that 3 cuts are not used either because the DPW for 3 cuts is lower than that for 4 cuts. Besides, 3 cuts provide less flexibility in wafer matching. More experiments have been done considering different wafer sizes, die sizes, defect models, etc. Since results are similar, they are not duplicated here.

Fig. 16
figure 16

Exploring the impact of number n of cuts on final production size of good 3D ICs produced by the sector symmetry and cut (SSCn) procedure

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Zhang, B., Agrawal, V.D. A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs. J Electron Test 30, 57–75 (2014). https://doi.org/10.1007/s10836-013-5429-1

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  • DOI: https://doi.org/10.1007/s10836-013-5429-1

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