Abstract
In the ongoing high-speed, high-tech sophistication in the technology of VLSI designs, Built-in Self-Test (BIST) is emerging as the essential element of the memory, which can be treated as the most essential ingredient of the System on Chip. The market is flooded with diverse algorithms exclusively intended for investigating the memory locations. LFSRs (Linear Feedback Shift Register) are employed extensively for engendering the memory addresses, so that they can be consecutively executed on the memory cores under experimentation. What we have attempted to put forward through this paper is a proposed LFSR based address generator with significant decrease in switching process for low power MBIST (Memory Built in Self Test). In this novel technique, the address models are produced by a blend of LFSR and a 2-bit pattern generator (Modified LFSR) and two distinct clock signals. With the efficient employ of the adapted architecture switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST. In this paper we have taken pains to design and stimulate the proposed address generator by means of Xilinx ISE tools and contrasted it with the switching activities of the conventional LFSR and BS-LFSR (Bit Swapping Linear Feedback Shift Register). The encouraging outcomes illustrate a significant reduction in switching activity, to the tune of 90 % plus of the entire dynamic power in relation to the traditional LFSR.
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References
Abu-Issa AS, Quigley SF (2009) Bit-swapping LFSR and scan-chain ordering: a novel technique for peak- and average-power reduction in scan-based BIST. IEEE Trans Comput-Aided Des Integr Circ Syst 28(5):755–759
Abu-Rahma MH, Anis M, Yoon SS (2010) Reducing SRAM power using fine-grained wordline pulse width control. IEEE Trans On Very Large Scale Integr (VLSI) Syst 18(3):356–364
Awad AN, Abu-Issa AS (2007) Low power address generator for memory built-in self test. Res Bull Jordan ACM III(II):52–56
Hsu C-L, Chen T-H (2009) Built-in self-test design for fault detection and fault diagnosis in SRAM-based FPGA. IEEE Trans Instrum Meas 58(7):2196–2208
Kumar TN, Lombardi F (2013) A novel heuristic method for application-dependent testing of a SRAM-based FPGA interconnect. IEEE Trans Comput 62(1):163–172
Marinissen EJ, Prince B, Keitel-Schulz D, Zorian Y (2005) Challenges in embedded memory design and test. Proc Design Autom Test Eur 52:722–727
Benini L, Bogliolo A, De Micheli G (2000) A survey of design techniques for system-level dynamic power management. IEEE Trans Very Large Scale Integr (VLSI) Syst 8(3):299–316
Mukherjee N, Pogiel A, Rajski J, Tyszer J (2011) BIST-based fault diagnosis for read-only memories. IEEE Trans Comput-Aided Des Integr Circ Syst 30(7):1072–1085
Muthammal R, Joseph DRKO (2011) Low power efficient built in self test. Proc IEEE Int Conf Microwaves Commun Antennas Electron Syst 7:1–5
NishaHaridas M, Devi N (2011) Efficient linear feedback shift register design for pseudo exhaustive test. Int J Electron Comput Technol 1:350–354
Noor NQ, Yusof Y, Sparon A (2009) Low area FSM-based memory BIST for synchronous SRAM. Proceedings of the international colloquium of Signal Processing and Its application, Kuala Lumpur, pp 409–412
Park Y, Park J, Han T, Kang S (2009) An effective programmable memory bist for embedded memory. IEICE Trans Inf Syst 92(12):808–818
Ravishankar-Reddy C, Zilani S, Sumalatha V (2012) Low power, Low-transition random pattern generator. Int J Eng Res Technol (IJERT) 1(5):1–6
Saraswathi T, Ragini K, Ganapathy Reddy C (2011) A review on power optimization of linear feedback shift register (LFSR) for low power built In self test (BIST). Int J Electronics Comput Technol 6:172–176
Sharma C (2011) Power reduction in VLSI chips by optimizing switching activity at test process, architecture & gate level. Int J Eng Sci Tech (IJEST) 3(4):3256–3259
Tehranipoor M, Nourani M, Ahmed N (2005) Low transition LFSR for BIST-based applications. Proceedings of the 14th Asian Test Symposium, pp 138–143
Van de Goor AdJ, Kukner H, Hamdioui S (2011) Optimizing memory BIST address generator implementations. 6th international conference on design & technology of integrated systems in nanoscale Era, pp 1–6, April
Wang S, Gupta SK (2002) DS-LFSR: a BIST TPG for Low switching activity. IEEE Trans Comput-Aided Des Integr Circ Syst 21(7):3
Wang W-L, Lee KJ (2005) A complete memory address generator for scan based march algorithms. Proceedings of the 2005 I.E. international workshop on memory technology, design, and testing (MTDT’05), Taipei, pp 83–88
Yarmolik SV, Yarmolik VN (2006) Modified gray and counter sequences for memory test address generation. Proceedings of International Conference MIXDES 2006 Gdynia, Poland, pp 572–576
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Krishna, K.M., Sailaja, M. Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers. J Electron Test 30, 77–85 (2014). https://doi.org/10.1007/s10836-014-5432-1
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DOI: https://doi.org/10.1007/s10836-014-5432-1