Abstract
Transistors within a gate take a finite amount of time to switch and hence there is always a propagation delay associated with it. These delays are evaluated by standard cell characterization techniques using EDA tools. However, these standard measurement methods tend to fail when simulating the design with practical values of slope and load and gives rise to the problem of negative or non-monotonic delays. Negative/non-monotonic delays lead to false positives during static timing analysis, synthesis and simulation of circuits and are undesirable. Hence, there is a need to implement new methods for characterization of propagation delay that will lead to more realistic monotonic delay values, ultimately achieving early timing closures. One such method of delay measurement based on actual switching thresholds has been proposed in this work.
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Acknowledgments
The authors would like to acknowledge Mr. Akhilesh Chandra Mishra and Mrs. Veena Krishnan Johar for their support and motivation. We would also like to thank Mr. Rajnish Garg for providing standard cell testcases and to Mr. Kapil Juneja for providing valuable feedbacks and reviews. Finally, a special mention of STMicroelectronics, Greater Noida for providing all the infrastructure required to carry out this work.
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Bhatnagar, P., Garg, S. Dynamic Threshold Delay Characterization Model for Improved Static Timing Analysis. J Electron Test 30, 495–504 (2014). https://doi.org/10.1007/s10836-014-5469-1
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DOI: https://doi.org/10.1007/s10836-014-5469-1