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Efficient LFSR Reseeding Based on Internal-Response Feedback

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Abstract

LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten test-application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a net-selection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 –2.75 % of internal nets and with 2.35 –4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.

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Acknowledgments

This work is partially supported by Ministry of Science and Technology of Taiwan under contract NSC102-2917-I-006-024, NSC102-2221-E-006-266-MY3, NSC101-2221-E-110-095-MY2 and MOST 103-2221-E-110-077-MY3.

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Authors and Affiliations

  1. Department of EE, National Cheng Kung University, Tainan, Taiwan

    Wei-Cheng Lien & Kuen-Jong Lee

  2. Department of EE, National Sun Yat-sen University, Kaohsiung, Taiwan

    Tong-Yu Hsieh

  3. Department of ECE, Duke University, Durham, NC, 27708, USA

    Krishnendu Chakrabarty

Authors
  1. Wei-Cheng Lien
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  2. Kuen-Jong Lee
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  3. Tong-Yu Hsieh
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  4. Krishnendu Chakrabarty
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Corresponding author

Correspondence to Tong-Yu Hsieh.

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Responsible Editor: J.-L. Huang

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Lien, WC., Lee, KJ., Hsieh, TY. et al. Efficient LFSR Reseeding Based on Internal-Response Feedback. J Electron Test 30, 673–685 (2014). https://doi.org/10.1007/s10836-014-5482-4

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  • DOI: https://doi.org/10.1007/s10836-014-5482-4

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