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One More Class of Sequential Circuits having Combinational Test Generation Complexity

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Abstract

The paper uses the concept of time expansion model to find the test generation for acyclic sequential circuits. Any acyclic sequential circuit without hold registers can be tested with combinational test generation complexity using this model. We show that for acyclic sequential circuits having hold registers, a subset of such circuits can also be tested with this complexity. We define the max-testable class of sequential circuits that includes both these groups. The paper also suggests an algorithm to find such class of circuits.

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Authors and Affiliations

  1. Computer Science and Engineering Department, Jadavpur University, Calcutta, 700032, India

    Debesh Kumar Das

  2. Faculty of Informatics, Osaka Gakuin University, Osaka, Japan

    Hideo Fujiwara

Authors
  1. Debesh Kumar Das
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  2. Hideo Fujiwara
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Corresponding author

Correspondence to Debesh Kumar Das.

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Responsible Editor: S. T. Chakradhar

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Das, D.K., Fujiwara, H. One More Class of Sequential Circuits having Combinational Test Generation Complexity. J Electron Test 31, 321–327 (2015). https://doi.org/10.1007/s10836-015-5527-3

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  • DOI: https://doi.org/10.1007/s10836-015-5527-3

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