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A New Approach to Model the Effect of Topology on Testing Using Boundary Scan

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Abstract

In this paper, a new analytical approach is presented to study the effect of commonly used topologies on the energy consumption and delay of on chip network (NOC) testing using IEEE 1149.1 standard. Here, first we model the energy of each module in JTAG standard, and then using test access port (TAP) controller state diagram and test algorithm, the totoal energy based on each topology is calculated. In addition, the number of clocks is calculated and together with the propagation delay of basic gates, the test time is modelled and calculated. Using the results we can choose the least energy-consuming and fastet topology in terms of testing. The modelling is verified using FPGA implementation.

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Authors and Affiliations

  1. Department of Computer Engineering, Faculty of Engineering, Islamic Azad University, Arak Branch, Arak, Markazi, Iran

    Farnaz Fotovatikhah & Mahdiar Ghadiry

  2. Department of Computer Engineering, Faculty of Engineering, Islamic Azad University, Ashtian Branch, Ashtian, Markazi, Iran

    Bahareh Naraghi

  3. Department of Computer Engineering, Islamic Azad University, Aligudarz Branch, Aligudarz, Iran

    Fatemeh Tavakoli

Authors
  1. Farnaz Fotovatikhah
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  2. Bahareh Naraghi
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  3. Fatemeh Tavakoli
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  4. Mahdiar Ghadiry
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Correspondence to Farnaz Fotovatikhah.

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Responsible Editor: M. Tehranipoor

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Fotovatikhah, F., Naraghi, B., Tavakoli, F. et al. A New Approach to Model the Effect of Topology on Testing Using Boundary Scan. J Electron Test 31, 301–310 (2015). https://doi.org/10.1007/s10836-015-5530-8

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  • DOI: https://doi.org/10.1007/s10836-015-5530-8

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