A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing

Abstract

The total logic activity produced in a digital circuit during testing, and hence the total energy consumed, is an invariant of a set of tests. Faster we consume this energy, shorter will the test time be. Thus, to minimize the test time we may maximize the power during test by using a dynamically selectable clock frequency. This idea is exploited in our solution for the problem of finding clock frequencies under the constraints of maximum allowable power and critical path delay. A very efficient but approximate kth-root solution finds k test clock frequencies, which are further optimized by a locally exhaustive search (LES) algorithm. Both solutions have an O(N×k) complexity for finding k clock frequencies when the test runs through N clock cycles, though kth-root solution is about two orders of magnitude faster to compute than LES. In practice, LES gives optimally minimum test time and is matched by the kth-root solution for k ≥ 10.