Abstract
In this paper, a new layout for SRAM 6T bitcell is presented. The new layout is a simple modification over the traditional 6T layout, but it has demonstrated better soft error tolerance over the traditional layout in radiation experiments. The area of the new layout is 31 % larger than the traditional layout. In TCAD simulation, it demonstrates over 2× smaller error cross section than the traditional layout. In alpha particle and proton experiments, its soft error rate can be reduced up to 73 % compared to the traditional layout.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Ahlbin JR, Atkinson NM, Gadlage MJ, Gaspard NJ, Bhuva BL, Loveless TD, Zhang EX, Chen L, Massengill LW (2011) Influence of n-well contact area on the pulse width of single-event transients. IEEE Trans Nucl Sci 58(6):2585–2590
Amusan OA, Massengill LW, Baze MP, Bhuva BL, Witulski AF, Black JD, Balasubramanian A, Casey MC, Black DA, Ahlbin JR, Reed RA, McCurdy MW (2008) Mitigation techniques for single-event-induced charge sharing in a 90-nm bulk CMOS process. Proc IEEE Int Reliability Phys Symp 468–472
Amusan OA, Massengill LW, Baze MP, Sternberg AL, Witulski AF, Bhuva BL, Black JD (2008) Single event upsets in deep-submicrometer technologies due to charge sharing. IEEE Trans Device Mater Reliab 8(3):582¨C–589
Amusan OA, Witulski AF, Massengill LW, Bhuva BL, Fleming PR, Alles ML, Sternberg AL, Black JD, Schrimpf RD (2006) Charge collection and charge sharing in a 130-nm CMOS technology. IEEE Trans Nucl Sci 53(6):3253–3258
Atkinson NM, Witulski AF, Holman WT (2011) Layout technique for single-event transient mitigation via pulse quenching. IEEE Trans Nucl Sci 58(3):885–890
Autran JL, Roche P, Sauze S, Gasiot G, Munteanu D, Loaiza P, Zampaolo M, Borel J (2009) Altitude and underground real-time SER characterization of CMOS 65 nm SRAM. IEEE Trans Nucl Sci 56(4):2258–2266
Bajura MA, Boulghassoul Y, Naseer R, DasGupta S, Witulski AF, Sondeen J, Stansberry SD, Draper JT, Massengill LW, Damoulakis JN (2007) Models and algorithmic limits for an ECC-based approach to hardening sub-100-nm SRAMs. IEEE Trans Nucl Sci 54(4):935–945
Black JD, Ball DR, Robinson WH, Fleetwood DM, Schrimpf RD, Reed RA, Black DA, Warren KM, Tipton AD, Dodd PE, Haddad NF, Xapsos MA, Kim HS, Friendlich M (2008) Characterizing SRAM single event upset in terms of single and multiple node charge collection. IEEE Trans Nucl Sci 55(6):2943–2947
Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43(6):2874–2878
Dodd PE, Massengill LW (2003) Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans Nucl Sci 50(3):583–602
Furutani K, Arimoto K, Miyamoto H, Kobayashi T, Yasuda K, Mashiko K (1989) A built-in hamming code ECC circuit for DRAM’s. IEEE J Solid State Circuits 24:50–56
Guo J, Xiao L, Mao Z (2014) Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology. IEEE Trans Circuits Syst I, Reg Papers 61(7):1994–2001
Lilja K, Bounasser M, Wen S, Wong R, Holst J, Gaspard N, Jagannathan S, Loveless D, Bhuva B (2013) Single-event performance and layout optimization of flip-flops in a 28-nm bulk technology. IEEE Trans Nucl Sci 60(4):2782–2788
Loveless TD, Jagannathan S, Reece T, Chetia J, Bhuva BL, Massengill LW, Wen S-J, Wong R, Rennie D (2011) Neutron- and proton-induced SEU error rates for D- and DICE flip/flop designs at a 40 nm technology node. IEEE Trans Nucl Sci 58(3):1008–1014
Olson BD, Ball DR, Warren KM, Massengill LW, Haddad NF, Doyle SE, McMorrow D (2005) Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design. IEEE Trans Nucl Sci 52(6):2132–2136
Robust Chip Inc. (2008) Layout method for soft-error hard electronics, and radiation hardened logic cell, USA US12/354,655, patent pending
Robust Chip Inc. (2009) Soft-error hard electronic circuit and layout, USA US12/763,139, patent pending
Robust Chip Inc. accuro user’s manual version 8.5
Schwank JR, Shaneyfelt MR, Dodd PE (2013) Radiation hardness assurance testing of microelectronic devices and integrated circuits: radiation environments, physical mechanisms, and foundations for hardness assurance. IEEE Trans Nucl Sci 60:2074–2100
Seifert N, Gill B, Zia V, Zhang M, Ambrose V (2007) On the scalability of redundancy based SER mitigation schemes. Proc IEEE Int Conf Integr Circuit Des Technol 1–9
Yamada J (1987) Selector-line merged built-in ECC technique for DRAM’s. IEEE J Solid State Circuits SC-22:868–873
Zhu M, Xiao L, Li S, Zhang Y, (2010) Efficient two-dimensional error codes for multiple bit upsets mitigation in memory. Proc IEEE 25th Int Symp Defect Fault Tolerance VLSI Syst 129–135
Acknowledgments
The authors would like to thank CMC Microsystems, Natural Science Engineering Research Council of Canada (NSERC), ASPIRE (CREATE program), Robust Chip Inc. (RCI) and NSFC under contract No. 61504038 for their support on this work.
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: K. K. Saluja
Rights and permissions
About this article
Cite this article
Li, L., Li, Y., Wang, H. et al. Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology. J Electron Test 31, 561–568 (2015). https://doi.org/10.1007/s10836-015-5549-x
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-015-5549-x