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Design and Implementation of an FPGA-Based Data/Timing Formatter

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Abstract

The data/timing formatter is a key module in automatic electronics test equipment; it formats the test data to the desired wave shape and places the timing edges at the designated locations. In this work, we investigate the design and implementation of the FPGA-based data/timing formatter. Compared to its ASIC counterpart, the FPGA-based formatter is more flexible because it can be reconfigured to best fit the target test specifications. However, routing uncertainty and limited types of available logic and interconnect resources also pose great challenges. This work proposes a formatter design that is suitable for FPGA implementation. Several high-linearity FPGA-based programmable delay lines are developed. According to its characteristics, each type of delay lines is assigned a different role in the formatter. The formatter is also equipped with a calibration unit to further improve the edge placement resolution and accuracy. A 100-Msps FPGA-based data/timing formatter with 20-ps edge placement resolution has been implemented on an FPGA development board to validate our ideas.

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Authors and Affiliations

  1. Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan

    Yu-Yi Chen & Jiun-Lang Huang

  2. OpenATE Inc., Taipei, Taiwan

    Yu-Yi Chen & Terry Kuo

  3. Industrial Technology Research Institute, Zhudong, Hsinchu, Taiwan

    Xuan-Lun Huang

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  1. Yu-Yi Chen
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  2. Jiun-Lang Huang
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  3. Terry Kuo
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  4. Xuan-Lun Huang
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Correspondence to Jiun-Lang Huang.

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Responsible Editor: V. D. Agrawal

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Chen, YY., Huang, JL., Kuo, T. et al. Design and Implementation of an FPGA-Based Data/Timing Formatter. J Electron Test 31, 549–559 (2015). https://doi.org/10.1007/s10836-015-5554-0

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  • DOI: https://doi.org/10.1007/s10836-015-5554-0

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