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Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM

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Abstract

Mobile Wide-I/O DRAMs are used in smartphones, tablets, handheld gaming consoles and other mobile devices. The main benefit of the Wide-I/O DRAM over its predecessors (such as LPDDRx DRAMs) is that it offers more bandwidth at lower power. In this paper, we propose a Wide-I/O DRAM built-in self-test design, named WIO-BIST including the local BIST (LO-BIST), global BIST (GL-BIST) and test interface structures, to support the fault detection in memory-die channels and TSVs. It should be noted that, a TSV test scheme is presented embedding the test procedure of TSVs into the memory-die channel test processes to significantly save the test time of TSVs. A logic die and 4 memory-dies stacking configuration is used to act as a dedicated circuit to demonstrate the feasibility of the proposed WIO-BIST design. Experimental results and comparisons show that the proposed WIO-BIST design has good performance in test time reduction with tiny extra area overhead penalty.

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Authors and Affiliations

  1. Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan, 31040, Republic of China

    Kun-Lun Luo, Ming-Hsueh Wu, Chun-Lung Hsu & Chen-An Chen

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  1. Kun-Lun Luo
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  2. Ming-Hsueh Wu
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  3. Chun-Lung Hsu
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Correspondence to Chun-Lung Hsu.

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Luo, KL., Wu, MH., Hsu, CL. et al. Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM. J Electron Test 32, 111–123 (2016). https://doi.org/10.1007/s10836-016-5570-8

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  • DOI: https://doi.org/10.1007/s10836-016-5570-8

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