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A Parallel Test Application Method towards Power Reduction

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Abstract

As the serial scan design has been one of the most popular methods in VLSI circuit test, power consumption during test increases significantly because of its inherent shift mode. To solve this problem, this paper proposes a novel test scheme, which makes a few improvements in the traditional scan architecture and adopts a new two-phase approach. First, each clock chain is activated in turn and the vectors for scan cells in the activated chain are applied in parallel within a test clock period. Second, after one pattern has been applied completely, all chains are activated to capture the response altogether. In addition, a compression algorithm is proposed to augment the parallelism of our method. Experimental results on benchmark circuits and industrial modules show that, compared with the traditional serial scan scheme, the proposed approach can reduce average power by 88.98% and peak power by 59.99% at acceptable area and wire length cost.

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References

  1. Baik DH, Saluja KK, Kajihara S (2004) Random Access Scan: A solution to test power, test data volume and test time. Proc. International Conference on VLSI Design, pp 883–888

  2. Basker P, Arulmurugan A (2012) Survey of low power testing of VLSI circuits. Proc. International Conference on Computer Communication and Informatics, pp 1–7

  3. Bhattacharya BB, Seth SC, Zhang S (2003) Double-tree scan: A novel low-power scan-path architecture. Proc. International Test Conference, pp 470–479

  4. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Springer Science+Business Media, New York

  5. Chandra A, Chakrabarty K (2001) Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip. Proc. Design Automation Conference, pp.166–169.

  6. Chandra A, Ng F, Kapur R, (2008) Low power Illinois scan architecture for simultaneous power and test data volume reduction. Proc. Design, Automation and Test in Europe Conference, pp. 462–467.

  7. Chou RM, Saluja KK, Agrawal VD (1994) Power constraint scheduling of tests. Proc. International Conference on VLSI Design, pp 271–274

  8. Chou RM, Saluja KK, Agrawal VD (1997) Scheduling tests for VLSI systems under power constraints. IEEE Transactions on VLSI Systems 5(2):175–185

  9. Enokimoto K, Wen X, Miyase K, Huang J-L, Kajihara S, Wang L-T (2013) On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression. Proc. 26th International Conference on VLSI Design, pp 279–284

  10. Flores P, Costa J, Neto H, Monteiro J, Marques-Silva J (1999) Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation, Proc. 12th International Conference on VLSI Design, pp 37–41

  11. Gerstendörfer S, Wunderlich H-J (1999) Minimized power consumption for scan-based BIST, Proc. International Test Conference, pp 77–84

  12. Girard P, Guiller L, Landrault C, Pravossoudovitch S (1999), A test vector ordering technique for switching activity reduction during test operation, Proc. 9th Great Lakes Symposium, pp 24-27

  13. Ando H (1980) Testing VLSI with random access scan, Proc. COMPCON, pp 50–52

  14. Jas A, Pouya B, Touba NA (2004) Test data compression technique for embedded cores using virtual scan chains. IEEE Transactions on VLSI Systems 12:775–781

    Article  Google Scholar 

  15. Le KT, Baik DH, Saluja KK (2007) Test time reduction to test for path-delay faults using enhanced random-access scan. Proc. International Conference on VLSI Design, pp 769–774

  16. Mudlapur AS, Agrawal VD, Singh AD (2005) A random access scans architecture to reduce hardware overhead. Proc. International Test Conference, Paper 15.1

  17. Mudlapur AS, Agrawal VD, Singh AD (2005) A novel random access scan flip-flop design. Proc. VLSI Design and Test Symp., pp 226-236

  18. Muthyala SS, Touba NA (2014) Improving test compression with scan feedforward techniques. Proc. International Test Conference, pp 1–10

  19. Nitin P, Sun X (2004) Design of a low-power D flip-flop for test-per-scan circuits. Proc. Canadian Conference on Electrical and Computer Engineering 2:777–780

  20. Saeed SM, Sinanoglu O (2011) Expedited response compaction for scan power reduction. Proc. IEEE VLSI Test Symposium, pp. 40–45.

  21. Sinanoglu O, Orailoglu A (2002) Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems, pp 325-333

  22. Vinay D, Chakravarty S, Pomeranz I, Reddy S (1998) Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans Comput Aided Des Integr Circuits Syst 17:1325–1333

    Article  Google Scholar 

  23. Wagner KD (1983) Design for testability in the AMDAHL 580, Proc. COMPCON, pp 384–388

  24. Wang S, Gupta SK (1997) ATPG for heat dissipation minimization during scan testing, Proc Design Automation Conf., pp 614–619

  25. Wohl P, Waicukauski JA., Colburn JE, Sonawane M (2014) Achieving extreme scan compression for SoC Designs, Proc. International Test Conference. pp.1–8

  26. Xiang D, Li KW, Sun JG, Fujiwara H (2007) Reconfigured scan forest for test application cost, test data volume and test power reduction. IEEE Trans Comput 56:557–562

    Article  MathSciNet  Google Scholar 

  27. Xiang D, Chen Z, Wang LT (2012). Scan flip-flop grouping to compress test data and compact test responses for broadside delay testing, ACM Trans. on Design Automation of Electronic Systems, Vol.17, Article No. 18.

  28. Yamato Y, Wen X, Kochte MA, Miyase K, Kajihara S, Wang L-T (2011) A novel scan segmentation design method for avoiding shift timing failure in scan testing, Proc. International test conference, pp 1–8

  29. Yu H, Han Y-H, Li X-W, Li H-W, Wen X-Q (2005) Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time, In Proc. 11th Pacific Rim International Symposium on Dependable Computing. 8.

  30. Yu H, Fu X, Fan X, Fujiwara H (2008) Localized random access scan: Towards low area and routing overhead, Proc. ASPDAC, pp 565-570

  31. Zhang X, Roy K (2000) Power reduction in test-per-scan BIST, Proc. On-Line Testing Workshop, pp 133–138

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Authors and Affiliations

  1. School of Computer, National University of Defense Technology, Changsha, 410073, China

    Ding Deng, Yang Guo & Zhentao Li

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  1. Ding Deng
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  2. Yang Guo
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  3. Zhentao Li
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Correspondence to Ding Deng.

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Responsible Editor: A. Orailoglu

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Deng, D., Guo, Y. & Li, Z. A Parallel Test Application Method towards Power Reduction. J Electron Test 33, 157–169 (2017). https://doi.org/10.1007/s10836-017-5656-y

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  • DOI: https://doi.org/10.1007/s10836-017-5656-y

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