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A Low Power Online Test Method for FPGA Single Solder Joint Resistance

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Abstract

Solder joint resistance monitoring is important for electronic system prognostics and system health management. It is noted that the typical built-in self-test method of FPGA solder joint has shortcomings of large power consumption, unavailability of test pins in FPGA’s functional design and possible difficulty in location arrangement of solder joint when two pins need to be measured simultaneously. To overcome these drawbacks, an online measuring method for single solder joint resistance with the constraints of limited pin number and low power consumption is proposed. The test model of the method is introduced in detail and the power consumption is theoretically analyzed. Furthermore, corresponding experimental platform is built based on a Spartan 6 FPGA and experiments are conducted. The test results show that the method can be used for online measurement of a solder joint’s resistance of an output pin in an FPGA design with very low power consumption.

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Correspondence to Nantian Wang.

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Responsible Editor: V. D. Agrawal

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Wang, N., Ma, X., Xu, X. et al. A Low Power Online Test Method for FPGA Single Solder Joint Resistance. J Electron Test 33, 775–780 (2017). https://doi.org/10.1007/s10836-017-5698-1

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  • DOI: https://doi.org/10.1007/s10836-017-5698-1

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