Abstract
To solve test challenges in nanometer CMOS technologies, a time-domain digital-intensive built-in tester for analog circuits is proposed. The compact tester allows characterizations of AC response and DC gain for various analog circuits which have a low-pass frequency characteristic. By applying ramp signals to stimulate the circuit under test and measuring slopes and time delays of its responses, the testing can be simple and robust over process-voltage-temperature variations. Also, it is well suited for nanometer technologies because of its digital-intensive implementation. The tester was fabricated in 65 nm standard CMOS process and occupies 0.026 mm2.
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Acknowledgments
The authors would like to thank TSMC, in particular Dr. E. Soenen for fabrication and Silicon Labs and TI for partial funding.
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Responsible Editors: M. Barragan and K. Huang
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Shi, C., Lee, S., Aguilar, S.S. et al. A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits. J Electron Test 34, 313–320 (2018). https://doi.org/10.1007/s10836-018-5713-1
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DOI: https://doi.org/10.1007/s10836-018-5713-1