Abstract
Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression scheme, which produces enormous switching activities during circuit testing, thereby causing high test power consumption for scan design. To solve the above thorny problem, LFSR reseeding-oriented low-power test-compression architecture is developed, and an optimized encoding algorithm is involved in conjunction with any LFSR-reseeding scheme to effectively reduce test storage and power consumption, it includes test cube-based block processing, dividing into hold partition sets and updating hold partition sets. The main contributions is to decrease logic transitions in scan chains and reduce specified bit in test cubes generated via LFSR reseeding. Experimental results demonstrate that the proposed scheme achieves a high test compression efficiency than the existing methods while significantly reduces test power consumption with acceptable area overhead for most Benchmark circuits.
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This research work was supported by National Natural Science Foundation of China (61001049), Beijing Natural Science Foundation (4172010) and Research Fund from Beijing Innovation Center for Future Chips (KYJJ2018009).
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Yuan, H., Zhou, C., Sun, X. et al. LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs. J Electron Test 34, 685–695 (2018). https://doi.org/10.1007/s10836-018-5756-3
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DOI: https://doi.org/10.1007/s10836-018-5756-3