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New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks

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Abstract

Finite state machine (FSM) is a critical part in digital processing devices used in Internet of Things (IoT) applications as it controls complete functionality of the device. The synthesis tool implements deterministic FSM by adding extra don’t care states/transitions during optimization. This additional insertion makes the FSM vulnerable to setup-time violation based fault injection (STVFI) and hardware Trojan attacks. The existing techniques are inefficient to completely mitigate these vulnerabilities and exhibit significant design overhead. Therefore, this paper presents a novel lightweight secure machine design technique that completely mitigates the vulnerabilities with minimum overhead. The paper first proposes a new metric to identify all types of vulnerable transitions (VTs) followed by a trustworthy FSM design algorithm and efficient vulnerability mitigation architecture (EVMA). Though our EVMA completely alleviates the vulnerabilities to STVFI and Trojan attacks, it slightly increases the overhead due to additional multiplexers. Hence, we also propose new secure FSM design algorithm and two new lightweight vulnerability mitigation architectures (LVMA-I and LIVMA-II) that control the FFs using existing clear and/or preset pins instead of multiplexers. The experimental results on AES and RSA encryption modules show that the proposed technique detects 100% VTs. Further, ASIC and FPGA implementation of the proposed LIVMA-II using Cadence RTL and Xilinx Vivado presents on an average 40%, 59.6%, and 51.1% reduced area, power and delay respectively compared to the well-known technique. Due to negligible design overhead, our technique is best suitable for designing secure controller of portable IoT devices.

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Authors and Affiliations

  1. ABV- Indian Institute of Information Technology and Management, Gwalior, India

    Vijaypal Singh Rathor & G. K. Sharma

  2. Thapar Institute of Engineering and Technology, Patiala, India

    Bharat Garg

Authors
  1. Vijaypal Singh Rathor
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  2. Bharat Garg
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  3. G. K. Sharma
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Correspondence to Vijaypal Singh Rathor.

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Responsible Editor: C. A. Papachristou

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Rathor, V.S., Garg, B. & Sharma, G.K. New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks. J Electron Test 34, 697–708 (2018). https://doi.org/10.1007/s10836-018-5762-5

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  • DOI: https://doi.org/10.1007/s10836-018-5762-5

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