Abstract
Globalization trend in integrated circuit design and manufacturing process has increased the vulnerability of integrated circuit. These vulnerabilities mainly caused by hardware Trojan have a serious impact on the security of integrated circuits. Although side-channel analysis approach is the most promising Trojan detection approach, nearly all side-channel analysis approaches rely heavily on the availability of golden chips, which are extremely difficult to obtain. In this paper, a golden layout model instead of fabricated golden chips is introduced for the practical application of hardware Trojan detection approaches. The simulated voltage variations generated from the golden layout model at different process corners serve as golden reference, thus fabricated golden chips are not required during detection. Further, silicon measurements are performed to obtain the voltage variations of fabricated chips, and a model calibration algorithm is utilized to calibrate the golden model in the presence of process variations and random noise. Finally, the Trojan detection is formulated as a two-class classification problem, and the Trojan is identified using the partitioning around medoids algorithm. Experimental results demonstrate that the similarities between the simulated traces and measured traces are greater than 98.81%, and the proposed approach distinguishes the Trojan chips correctly even under ± 15% process variation.
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This work is funded partially by the National Natural Science Foundation of China (61832018) and China Postdoctoral Science Foundation (2019TQ0167).
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Liu, Y., He, J., Ma, H. et al. Hardware Trojan Detection Leveraging a Novel Golden Layout Model Towards Practical Applications. J Electron Test 35, 529–541 (2019). https://doi.org/10.1007/s10836-019-05816-w
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DOI: https://doi.org/10.1007/s10836-019-05816-w