Skip to main content
Log in

Hardware Trojan Detection Leveraging a Novel Golden Layout Model Towards Practical Applications

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Globalization trend in integrated circuit design and manufacturing process has increased the vulnerability of integrated circuit. These vulnerabilities mainly caused by hardware Trojan have a serious impact on the security of integrated circuits. Although side-channel analysis approach is the most promising Trojan detection approach, nearly all side-channel analysis approaches rely heavily on the availability of golden chips, which are extremely difficult to obtain. In this paper, a golden layout model instead of fabricated golden chips is introduced for the practical application of hardware Trojan detection approaches. The simulated voltage variations generated from the golden layout model at different process corners serve as golden reference, thus fabricated golden chips are not required during detection. Further, silicon measurements are performed to obtain the voltage variations of fabricated chips, and a model calibration algorithm is utilized to calibrate the golden model in the presence of process variations and random noise. Finally, the Trojan detection is formulated as a two-class classification problem, and the Trojan is identified using the partitioning around medoids algorithm. Experimental results demonstrate that the similarities between the simulated traces and measured traces are greater than 98.81%, and the proposed approach distinguishes the Trojan chips correctly even under ± 15% process variation.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

References

  1. Agrawal D, Baktir S, Karakoyunlu D, Rohatgi P, Sunar B (2007) Trojan detection using ic fingerprinting. In: Proceedings of the 2007 IEEE Symposium on Security and Privacy (SP’07), IEEE, pp 296–310

  2. Alexandridis A, Chondrodima E, Giannopoulos N, Sarimveis H (2016) A fast and efficient method for training categorical radial basis function networks. IEEE Transactions on Neural Networks and Learning Systems 28(11):2831–2836

    Article  Google Scholar 

  3. Bai Y, Li H, Zhang Y (2016) A hybrid model for congestion prediction in hf spectrum based on complete ensemble empirical mode decomposition. In: Proceedings of the 2016 CIE International Conference on Radar (RADAR), IEEE, pp 1–5

  4. Balasch J, Gierlichs B, Verbauwhede I (2015) Electromagnetic circuit fingerprints for hardware trojan detection. In: Proceedings of the 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC), IEEE, pp 246–251

  5. Bao C, Forte D, Srivastava A (2015) Temperature tracking: toward robust run-time detection of hardware trojans. IEEE Trans Comput Aided Des Integr Circuits Syst 34(10):1577–1585

    Article  Google Scholar 

  6. Bhasin S, Danger JL, Graba T, Mathieu Y, Fujimoto D, Nagata M (2014) Physical security evaluation at an early design-phase: A side-channel aware simulation methodology. In: Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems (ES4CPS’14), ACM, p 13

  7. Brier E, Clavier C, Olivier F (2004) Correlation power analysis with a leakage model. In: Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems (CHES), Springer, pp 16–29

  8. Calibre. https://www.cadence.com/. Accessed December 27, 2018

  9. Chakraborty A, Mazumdar B, Mukhopadhyay D (2017) A combined power and fault analysis attack on protected grain family of stream ciphers. IEEE Trans Comput Aided Des Integr Circuits Syst 36(12):1968–1977

    Article  Google Scholar 

  10. Du D, Narasimhan S, Chakraborty RS, Bhunia S (2010) Self-referencing: a scalable side-channel approach for hardware trojan detection. In: Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems (CHES), Springer, pp 173–187

  11. Du D, Narasimhan S, Chakraborty RS, Bhunia S (2010) Self-referencing: a scalable side-channel approach for hardware trojan detection. In: Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems (CHES), Springer, pp 173–187

  12. Elnaggar R, Chakrabarty K (2018) Machine learning for hardware security: opportunities and risks. J Electron Test 34(2):183– 201

    Article  Google Scholar 

  13. Exurville I, Zussa L, Rigaud JB, Robisson B (2015) Resilient hardware trojans detection based on path delay measurements. In: Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), IEEE, pp 151–156

  14. Fujimoto D, Nagata M, Katashita T, Sasaki A, Hori Y, Satoh A (2011) A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. In: Proceedings of the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), IEEE, pp 87–92

  15. Global Foundries. https://www.globalfoundries.com/. Accessed December 27, 2018

  16. Han HG, Lu W, Hou Y, Qiao JF (2018) An adaptive-pso-based self-organizing rbf neural network. IEEE transactions on Neural Networks and Learning Systems 29(1):104–117

    Article  MathSciNet  Google Scholar 

  17. Hasegawa K, Yanagisawa M, Togawa N (2017) Trojan-net feature extraction and its application to hardware-trojan detection for gate-level netlists using random forest. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 100(12):2857–2868

    Article  Google Scholar 

  18. Hayt WH, Kemmerly JE, Durbin SM (2002) Engineering Circuit Analysis. McGraw-Hill, New York

    Google Scholar 

  19. He C, Hou B, Wang L, En Y, Xie S (2015) A failure physics model for hardware trojan detection based on frequency spectrum analysis. In: Proceedings of the 2015 IEEE International Reliability Physics Symposium (IRPS), pages PR.1.1–PR.1.4

  20. He J, Zhao Y, Guo X, Jin Y (2017) Hardware trojan detection through chip-free electromagnetic side-channel statistical analysis. IEEE Trans Very Large Scale Integr VLSI Syst 25(10):2939–2948

    Article  Google Scholar 

  21. Hoque T, Narasimhan S, Wang X, Mal-Sarkar S, Bhunia S (2017) Golden-free hardware trojan detection with high sensitivity under process noise. J Electron Test 33(1):107–124

    Article  Google Scholar 

  22. Hossain FS, Yoneda T, Inoue M, Orailoglu A (2017) Detecting hardware trojans without a golden ic through clock-tree defined circuit partitions. In: Proceedings of the 2017 22nd IEEE European Test Symposium (ETS), pp 1–6

  23. HSPICE. https://www.synopsys.com/. Accessed December 27, 2018

  24. Jin Y, Makris Y (2008) Hardware trojan detection using path delay fingerprint. In: Proceedings of the 2008 IEEE International workshop on hardware-oriented security and trust (HOST), IEEE, pp 51–57

  25. Kim M, Chung E, Yoon S (2009) High-speed post-layout logic simulation using quasi-static clock event evaluation. IEEE Trans Comput Aided Des Integr Circuits Syst 28(8):1274–1278

    Article  Google Scholar 

  26. Lamech C, Plusquellic J (2012) Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure. In: Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp 75–82

  27. Lecomte M, Fournier J, Maurine P (2017) An on-chip technique to detect hardware trojans and assist counterfeit identification. IEEE Trans Very Large Scale Integr VLSI Syst 25(12):3317–3330

    Article  Google Scholar 

  28. Leung CS, Wan WY, Feng R (2017) A regularizer approach for rbf networks under the concurrent weight failure situation. IEEE Transactions on Neural Networks and Learning Systems 28(6):1360–1372

    Article  Google Scholar 

  29. Lin L, Burleson W, Paar C (2009) Moles: malicious off-chip leakage enabled by side-channels. In: Proceedings of the 2009 international conference on computer-aided design (ICCAD), ACM, pp 117–122

  30. Liu Y, Huang Y, Makris Y (2014) Hardware trojan detection through golden chip-free statistical side-channel fingerprinting. In: Proceedings of the 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), pp 1–6

  31. Liu L, Pokharel R (2014) Post-layout simulation time reduction for phase-locked loop frequency synthesizer using system identification techniques. IEEE Trans Comput Aided Des Integr Circuits Syst 33(11):1751–1755

    Article  Google Scholar 

  32. Menichelli F, Menicocci R, Olivieri M, Trifiletti A (2008) High-level side-channel attack modeling and simulation for security-critical systems on chips. IEEE Trans Dependable Secure Comput 5(3):164–176

    Article  Google Scholar 

  33. Narasimhan S, Du D, Chakraborty RS, Paul S, Wolff F, Papachristou C, Roy K, Bhunia S (2010) Multiple-parameter side-channel analysis: a non-invasive hardware trojan detection approach. In: Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp 13–18

  34. Narasimhan S, Du D, Chakraborty RS, Paul S, Wolff FG, Papachristou CA, Roy K, Bhunia S (2013) Hardware trojan detection by multiple-parameter side-channel analysis. IEEE Trans Comput 62(11):2183–2195

    Article  MathSciNet  MATH  Google Scholar 

  35. Narasimhan S, Wang X, Du D, Chakraborty RS, Bhunia S (2011) Tesr: a robust temporal self-referencing approach for hardware trojan detection. In: Proceedings of the 2011 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp 71–74

  36. Ngo XT, Exurville I, Bhasin S, Danger JL, Guilley S, Najm Z, Rigaud JB, Robisson B (2015) Hardware trojan detection by delay and electromagnetic measurements. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium, pp 782–787

  37. Nowroz AN, Hu K, Koushanfar F, Reda S (2014) Novel techniques for high-sensitivity hardware trojan detection using thermal and power maps. IEEE Trans Comput Aided Des Integr Circuits Syst 33(12):1792–1805

    Article  Google Scholar 

  38. Park HS, Jun CH (2009) A simple and fast algorithm for k-medoids clustering. Expert Systems with Applications 36(2):3336–3341

    Article  Google Scholar 

  39. Peeters E, Standaert FX, Quisquater JJ (2007) Power and electromagnetic analysis: improved model, consequences and comparisons. Integr VLSI J 40(1):52–60

    Article  Google Scholar 

  40. Rad R, Plusquellic J, Tehranipoor M (2008) Sensitivity analysis to hardware trojans using power supply transient signals. In: Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust (HOST), pp 3–7

  41. Raitoharju J, Kiranyaz S, Gabbouj M (2015) Training radial basis function neural networks for classification via class-specific clustering. IEEE Transactions on Neural Networks and Learning Systems 27(12):2458–2471

    Article  Google Scholar 

  42. Seo J, Ma H, Saha T (2018) On savitzkycgolay filtering for online condition monitoring of transformer on-load tap changer. IEEE Trans Power Delivery 33(4):1689–1698

    Article  Google Scholar 

  43. Söll O, Korak T, Muehlberghuber M (2014) Em-based detection of hardware trojans on fpgas. In: Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp 84–87

  44. Tiri K, Verbauwhede I (2005) A vlsi design flow for secure side-channel attack resistant ics. In: Proceedings of the Design, Automation and Test in Europe (DATE), Vol 3. pp 58–63

  45. Wu TF, Ganesan K, Hu YA, Wong HP, Wong S, Mitra S (2016) Tpad: hardware trojan prevention and detection for trusted integrated circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 35(4):521–534

    Article  Google Scholar 

  46. Wei S, Meguerdichian S, Potkonjak M (2011) Malicious circuitry detection using thermal conditioning. IEEE Trans Inf Forensics Secur 6(3):1136–1145

    Article  Google Scholar 

  47. Xue H, Ren S (2018) Self-reference-based hardware trojan detection. IEEE Trans Semicond Manuf 31 (1):2–11

    Article  Google Scholar 

  48. Xue M, Wang J, Hux A (2016) An enhanced classification-based golden chips-free hardware trojan detection technique. In: Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), pp 1–6

  49. Yoshimizu N (2014) Hardware trojan detection by symmetry breaking in path delays. In: Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp 107–111

  50. Yu D, Liu G, Guo M, Liu X (2018) An improved k-medoids algorithm based on step increasing and optimizing medoids. Expert Syst Appl 92:464–473

    Article  Google Scholar 

  51. Zarrinchian G, Zamani MS (2017) Latch-based structure: a high resolution and self-reference technique for hardware trojan detection. IEEE Trans Comput 66(1):100–113

    Article  MathSciNet  Google Scholar 

  52. Zhao X, Han L, Feng Z (2015) A performance-guided graph sparsification approach to scalable and robust spice-accurate integrated circuit simulations. IEEE Trans Comput Aided Des Integr Circuits Syst 34(10):1639–1651

    Article  Google Scholar 

  53. Zheng Y, Yang S, Bhunia S (2016) Semia: self-similarity-based ic integrity analysis. IEEE Trans Comput Aided Des Integr Circuits Syst 35(1):37–48

    Article  Google Scholar 

Download references

Acknowledgments

This work is funded partially by the National Natural Science Foundation of China (61832018) and China Postdoctoral Science Foundation (2019TQ0167).

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Yiqiang Zhao.

Additional information

Responsible Editor: M. Hsiao

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Liu, Y., He, J., Ma, H. et al. Hardware Trojan Detection Leveraging a Novel Golden Layout Model Towards Practical Applications. J Electron Test 35, 529–541 (2019). https://doi.org/10.1007/s10836-019-05816-w

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-019-05816-w

Keywords

Navigation