Abstract
In this paper, a latch design with single node immunity to single event upsets during the hold state is proposed. This structure is based on the original Quatro latch and have two more redundant storage nodes. Compared with the reference, this structure is able to recover if any of these nodes is struck by ion particles during the hold state and it also has improved multiple node upset performance. Simulations and laser experiment results have validated its effectiveness of SEU resilience by having a larger laser energy threshold for upset and lower SEU error counts compared with the reference. The power, area, and delay penalties are 86%, 48%, and 64% respectively; they are as a consequence of six more transistors added to the latch.
Similar content being viewed by others
References
Amusan OA, Massengill LW, Baze MP, Bhuva BL, Witulski AF, SandeepanDasGupta AL, Sternberg PR, Fleming CC, Heath MLA (2007) Directional sensitivity of single event upsets in 90 nm CMOS due to charge sharing. IEEE Trans Nucl Sci 54(6):2584–2589
Bastos RP, Sicard G, Kastensmidt F, Renaudin M, Reis R (2010) Evaluating transient-fault effects on traditional C-element's implementations, Proc. IEEE International On-line Testing Symposium
Baumann RC (2005) Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans Device Mater Reliab 5(3):305–316
Black JD, Sternberg AL, Alles ML, Witulski AF, Bhuva BL, Massengill LW, Benedetto JM, Baze MP, Wert JL, Hubert MG (2005) HBD layout isolation techniques for multiple node charge collection mitigation. IEEE Trans Nucl Sci 52(6):2536–2541
Buchner S, Warner J, McMorrow D, Miller F, Morand S, Pouget V, Larue C, Adell P, Allen G (2012) Comparison of single event transients generated at four pulsed-laser test facilities-NRL, IMS, EADS, JPL. IEEE Trans Nucl Sci 59(4):988–998
Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43(6):2874–2878
David R, David L, Manoj S, Bhuva BL, Jagannathan S, Wen S-J, Wong R (2012) Performance, Metastability, and soft-error robustness trade-offs for Flip-flops in 40 nm CMOS. IEEE Trans Circuits Syst Regul Pap 59(8):1626–1634
Dhillon YS, Diril AU, Chatterjee A, Singh AD (2006) Analysis and optimization of nanometer CMOS circuits for soft-error tolerance. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(5):514–524
Dodd PE, Massengill LW (2003) Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans Nucl Sci 50(3):583–602
Gardiner KT, Yakovlev A, Bystrov A (2007) A C-element latch scheme with increased transient fault tolerance for asynchronous circuits. Proc IEEE International On-line Testing Symposium
Grando CN, Lisboa CA, Moreira AF, Carro L (2009) Invariant checkers: An efficient low cost technique for run-time transient errors detection, Proc IEEE International On-line Testing Symposium
Jagannathan S, Loveless TD, Bhuva BL, Wen S-J, Wong R, Sachdev M, Rennie D, Massengill LW (2011) Single-event tolerant Flip-flop design in 40-nm bulk CMOS technology. IEEE Trans Nucl Sci 58(6):3033–3037
Jahinuzzaman SM, Rennie DJ, Sachdev M (2009) A soft error tolerant 10T SRAM bit-cell with differential read capability. IEEE Trans Nucl Sci 56(6):3768–3773
Laird JS, Toshio H, Shinobu O, Hisayoshi I, Allan J (2007) Comparison of above bandgap laser and MeV ion induced single event transients in high-speed Si photonic devices. IEEE Trans Nucl Sci 53(6):3312–3320
Lee HK, Lilja K, Bounasser M, Relangi P, Linscott IR, Inan US, Mitra S (2010) LEAP: layout design through error-aware transistor positioning for soft-error resilient sequential cell design, Proc Reliability Physics Symposium IEEE 203–212
Messenger GC (1982) Collection of charge on junction nodes from ion tracks. IEEE Trans Nucl Sci 29(6):2024–2031
Miller F, Buard N, Carriere T, Dufayel R, Gaillard R, Poirot P, Palau J-M, Sagnes B, Fouillat P (2004) Effects of beam spot size on the correlation between laser and heavy ion SEU testing. IEEE Trans Nucl Sci 51(6):3708–3715
Nicolaidis M (2005) Design for soft error mitigation. IEEE Trans Device Mater Reliab 5(3):405–418
Olson BD, Amusan OA, DasGupta S, Massengill LW, Witulski AF, Bhuva BL, Alles ML, M K, Warren DRB (2007) Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology. IEEE Trans Nucl Sci 54(4):894–897
Prasanth V, Singh V, Parekhji R (2011) Reduced overhead soft error mitigation using error control coding techniques, Proc On-line Testing Symposium IEEE
Schwank JR, Shaneyfelt MR, McMorrow D, Cavrois VF, Dodd P, Heidel DF, Marshall PW, Pellish JA, LaBel KA, Rodbell KP, Hakey M, Flores RS, Swanson SE, Dalton SM (2010) Estimation of heavy-ion LET thresholds in advanced SOI IC technologies from two-photon absorption laser measurements. IEEE Trans Nucl Sci 57(4):1827–1834
Wang H-B, Chen L, Liu R, Li Y-Q, Kauppila JS, Bhuva BL, Lilja K, Wen S-J, Wong R, Fung R, Baeg S (2016) An area efficient stacked latch design tolerant to SEU in 28 nm FDSOI technology. IEEE Trans Nucl Sci 63(6):3003–3009
Xilinx (2018) Zynq-7000 SoC technical reference manual. [Online]. Available: https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
Yu YT, Han JW, Feng GQ (2015) Correction of single event Latchup rate prediction using pulsed laser mapping test. IEEE Trans Nucl Sci 62(2):565–570
Acknowledgments
This work is supported by NSFC through Hohai University (61504038) and through Innovation Foundation of Radiation Application, China Institute of Atomic Energy (KFZC2018040205). This is also supported by Changzhou Sci & Tech Program (Grant no. CZ20180003).
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: C. A. Papachristou
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Dai, X., Wang, H., Chu, J. et al. A Single Event Upset Resilient Latch Design with Single Node Upset Immunity. J Electron Test 35, 909–916 (2019). https://doi.org/10.1007/s10836-019-05823-x
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-019-05823-x