Abstract
Several applications such as signal processing, multimedia and big data analysis exhibit computational error tolerance. This tolerance can be exploited to achieve efficient designs by sacrificing accuracy. Therefore, approximate computing presents a new design paradigm that smashes the traditional belief of error-free computations and provides efficient design with quality metrics specific to an application. The multiplication operation significantly determines the performance of the core due to the compute intensive operation. Therefore, this paper proposes a novel leading one bit based approximate (LoBA) multiplier architecture that selects k-bits from n-bit inputs (k ≤ n/4) based on leading one bit (LOB) and then computes approximate product based of these small input. The accuracy is further improved by selecting next k-bits based on LOB position and considering the partial product for computing final product. Four imprecise LoBA multipliers are presented that provide trade-off between accuracy and performance. Finally, the effectiveness of the proposed architectures is shown over the existing multipliers as standalone arithmetic unit and in the application by implementing Gaussian smoothing filters. The proposed 16-bit LoBA0 and LoBA1 designs reduce power consumption by 64.2% and 32.9%, respectively over the existing multiplier architecture.
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References
Babič Z, Avramovič A, Bulič P (2008) “An iterative mitchell’s algorithm based multiplier”. In: 2008 IEEE International Symposium on Signal Processing and Information Technology. IEEE, pp 303–308
Garg B, Bharadwaj NK, Sharma G (2014) “Energy scalable approximate DCT architecture trading quality via boundary error-resiliency”. In: 2014 27th IEEE International System-on-Chip Conference (SOCC), IEEE pp 306–311
Garg B, Sharma G (2016) “Low power signal processing via approximate multiplier for error-resilient applications”. In: 2016 11th International Conference on Industrial and Information Systems (ICIIS), IEEE, pp 546–551
Garg B, Sharma G (2016) A quality-aware energy-scalable Gaussian smoothing filter for image processing applications. Microprocess Microsyst 45:1–9
Garg B, Dutt S, Sharma G (2016) Bit-width-aware constant-delay run-time accuracy programmable adder for error-resilient applications. Microelectron J 50:1–7
Garg B, Sharma G (2017) ACM: An energy-efficient accuracy configurable multiplier for error-resilient applications. J Electron Test 33(4):479–489
Han J, Orshansky M (2013) “Approximate computing:, An emerging paradigm for energy-efficient design”. In: Test Symposium (ETS), 2013 18th IEEE European, pp 1–6
Hashemi S, Bahar R, Reda S (2015) “DRUM:, A dynamic range unbiased multiplier for approximate applications”. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. IEEE Press, pp 418–425
Jaiswal A, Garg B, Kaushal V, Sharma G (2015) “SPAA-aware 2D Gaussian smoothing filter design using efficient approximation techniques”. In: VLSI Design (VLSID), 2015 28th International Conference on, IEEE, pp 333–338
Kahng A, Kang S (2012) “Accuracy-configurable adder for approximate arithmetic designs”. In: Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, pp 820–825
Kulkarni P, Gupta P, Ercegovac M (2011) “Trading accuracy for power with an underdesigned multiplier architecture”. In: VLSI Design (VLSI Design), 2011 24th International Conference on, pp 346–351
Kyaw KY, Goh W-L, Yeo K-S (2010) “Low-power high-speed multiplier for error-tolerant application”. In: Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference pp 1–4
Liang J, Han J, Lombardi F (2011) New metrics for the reliability of approximate and probabilistic adders. Computers, IEEE Transactions on 99:1–1
Liu C, Han J, Lombardi F (2014) “A low-power, high-performance approximate multiplier with configurable partial error recovery”. In: Proceedings of the conference on Design, Automation & Test in Europe, European Design and Automation Association, p 95
Mclaren DJ (2003) “Improved mitchell-based logarithmic multiplier for low-power dsp applications”. In: IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings. IEEE, pp 53–56
Mitchell JN (1962) Computer multiplication and division using binary logarithms. IRE Trans Electron Comput 4:512–517
Mittal S (2016) A survey of techniques for approximate computing. ACM Computing Surveys (CSUR) 48 (4):62
Moreau T, Sampson A, Ceze L (2015) Approximate computing: Making mobile systems more efficient. IEEE Pervasive Computing 14(2):9–13
Narayanamoorthy S, Moghaddam HA, Liu Z, Park T, Kim NS (2015) “Energy-efficient approximate multiplication for digital signal processing and classification applications”. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol 23, pp 1180–1184
Vahdat S, Kamal M, Afzali-Kusha A, Pedram M (2017) LETAM: A low energy truncation-based approximate multiplier. Computers & Electrical Engineering 63:1–17
Vahdat S, Kamal M, Afzali-Kusha A, Pedram M (2019) “TOSAM: An Energy-efficient truncation-and rounding-based scalable approximate multiplier,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wang Z, Bovik A, Sheikh H, Simoncelli E (2004) Image quality assessment: from error visibility to structural similarity. Image Processing, IEEE Transactions on 13(4):600–612
Zendegani R, Kamal M, Bahadori M, Afzali-Kusha A, Pedram M (2017) ROBA Multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25(2):393–401
Zhu N, Goh WL, Zhang W, Yeo KS, Kong ZH (2010) “Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing”. Very Large Scale Integration (VLSI) Systems, IEEE Transactions 18(8):1225–1229
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Garg, B., Patel, S.K. & Dutt, S. LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing. J Electron Test 36, 429–437 (2020). https://doi.org/10.1007/s10836-020-05883-4
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DOI: https://doi.org/10.1007/s10836-020-05883-4