Abstract
With the technology node scaling down into nanometer range, the effect of parasitic inductance and capacitance between the interconnect lines on predicting single event crosstalk (SEC) has to be considered. An analytical model is proposed to evaluate SEC in nanometer CMOS circuits based on the equation circuit of single event transient and RLC distributed model of interconnect. The transfer function of the arbitrary segment of interconnects is deduced by applying KCL and KVL laws in Laplace domain. The accurate expression of SEC voltage is achieved by the operation of matrix polynomial. For convenient calculation, a third-order exponential model is used to describe the SEC voltage approximately. The simulation results at the technology nodes of 22 nm, 32 nm, 45 nm, 65 nm, and 90 nm show that in comparison to previous work, the analytical model has a significantly improved accuracy with an average error of only 2.19%.
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This work was supported by the National Natural Science Foundation of China (Grant No.11975311, 11405270).
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Liu, B., Cai, L. & Liu, X. An Analytic Model for Predicting Single Event (SE) Crosstalk of Nanometer CMOS Circuits. J Electron Test 36, 461–467 (2020). https://doi.org/10.1007/s10836-020-05891-4
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DOI: https://doi.org/10.1007/s10836-020-05891-4