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Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults

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Abstract

Radiation-induced single transient faults (STFs) are expected to evolve into multiple transient faults (MTFs) at nanoscale CMOS technology nodes. For this reason, the reliability evaluation of logic circuits in the presence of MTFs is becoming an important aspect of the design process of deep submicron and nanoscale systems. However, an accurate evaluation of the reliability of large-scale and very large-scale circuits is both very complex and time-consuming. Accordingly, this paper presents a novel soft error reliability calculation approach for logic circuits based on a probability distribution model. The correctness or incorrectness of individual logic elements are regarded as random events obeying Bernoulli distribution. Subsequently, logic element conversion-based fault simulation experiments are conducted to analyze the logical masking effects of the circuit when one logic element fails or when two elements fail simultaneously. On this basis, the reliability boundaries of the logic circuits can efficiently be calculated using the proposed probability model and fault simulation results. The proposed solution can obtain an accurate reliability range through single fault and double faults simulations with small sample sizes, and also scales well with the variation of the error rate of the circuit element. To validate the proposed approach, we have calculated the reliability boundaries of ISCAS’85, ISCAS’89, and ITC’99 benchmark circuits. Statistical analysis and experimental results demonstrate that our method is effective and scalable, while also maintaining sufficiently close accuracy.

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Authors and Affiliations

  1. School of Computer and Communication Engineering, Changsha University of Science and Technology, Changsha, 410114, HN, China

    Shuo Cai, Binyong He, Weizheng Wang & Fei Yu

  2. School of Computer, Guangdong University of Technology, Guangzhou, 510006, GD, China

    Peng Liu

  3. School of Automotive and Mechanical Engineering, Changsha University of Science and Technology, Changsha, 410114, HN, China

    Lairong Yin

  4. Key Laboratory of Silicon Device Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China

    Bo Li

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  1. Shuo Cai
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Correspondence to Shuo Cai.

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This work was supported by the National Natural Science Foundation of China (NSFC) (Grant No.61702052, No.61504013, No.61804037), Hunan Provincial Natural Science Foundation of China (Grant No. 2020JJ4622, No. 2019JJ50648), and the Scientific Research Fund of Hunan Provincial Education Department (Grant No.18A137, No.17B011).

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Cai, S., He, B., Wang, W. et al. Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults. J Electron Test 36, 469–483 (2020). https://doi.org/10.1007/s10836-020-05898-x

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  • DOI: https://doi.org/10.1007/s10836-020-05898-x

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