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A Fault Verification Method Based on the Substitution Theorem and Voltage-Current Phase Relationship

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Abstract

This paper presents a new fault verification method for diagnosis of parametric faults in linear analog circuits. Although there has been much research on fault verification methods there are still some open problems, such as low testability and extensive computational procedures in the case of multiple faults. The proposed method is based on the substitution theorem. It deals with the branch currents and voltages as opposed to the standard branch fault verification method, which only considers the branch current deviations. In this way, both the magnitude and phase angle of the faulty currents are taken into consideration, allowing us to check the physical meaning of the faulty currents. The fault detection procedure is based on the frequency domain measurements and the use of the sinusoidal excitation. The presented approach enhances the diagnosability, reduces on-line computations and decreases the number of required test nodes by one. The feasibility of the method is demonstrated through measurement experiments.

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References

  1. Liu RW (2012) Testing and diagnosis of analog circuits and systems. Springer-Verlag New York Inc., USA

    Google Scholar 

  2. Robotycki A, Zielonko R (2002) Fault diagnosis of analog piecewise linear circuits based on homotopy. IEEE Trans Instrum Meas 51(4):876–881

    Article  Google Scholar 

  3. Tadeusiewicz M, Halgas S (2012) Multiple soft fault diagnosis of nonlinear circuits using the continuation method. J Elect Testing: Theory Appl (JETTA) 28(4):487–493

    Article  Google Scholar 

  4. Worsman M, Wong MWT (2000) Non-linear analog circuit fault diagnosis with large change sensitivity. Int J Circuit Theory Appl 28(3):281–303

    Article  Google Scholar 

  5. Fedi G, Giomi R, Luchetta A, Manetti S, Piccirilli M (1998) On the application of symbolic techniques to the multiple fault location in low testability analog circuits. IEEE Trans Circuits Syst II: Analog Digital Signal Process 45(10):1383–1388

    Article  Google Scholar 

  6. Filippetti F, Artioli M (2002) Cycling verify: fault diagnosis for linear analog circuits based on symbolic calculus and interval algebra. In: Proceedings of the 19th IEEE Instrumentation and Measurement Technology Conference, 1, pp 589–594

  7. Tadeusiewicz M, Korzybski M (2000) A method for fault diagnosis in linear electronic circuits. Int J Circuit Theory Appl 28(3):245–262

    Article  Google Scholar 

  8. Tadeusiewicz M, Hałgas S (2006) An algorithm for multiple fault diagnosis in analog circuits. Int J Circuit Theory Appl 34(6):607–615

    Article  Google Scholar 

  9. Huang Z, Lin C, Liu R (1983) Node-fault diagnosis and a Design of Testability. IEEE Trans Circuits Syst 30(5):257–265

    Article  MathSciNet  Google Scholar 

  10. Wu Y, Tong BS (1990) The effective range of k-fault diagnosis of linear circuits. J Electron (China) 7(3):207–214

    Article  Google Scholar 

  11. Sun Y (2008) Test and diagnosis of analogue, mixed-signal and RF integrated circuits: the system on chip approach, chapter 1. The Institute of Engineering and Technology, London, pp 1–36

    Google Scholar 

  12. Sun Y (1988) Bilinear relations for fault diagnosis of linear circuits. Proceedings of CSEE and IEE Beijing Section National Conference on CAA and CAD, Zhejiang

    Google Scholar 

  13. Yang C, Tian S, Liu Z, Huang J, Chen F (2013) Fault modeling on complex plane and tolerance handling methods for analog circuits. IEEE Trans Instrum Meas 62(10):2730–2738

    Article  Google Scholar 

  14. Hong-zhi H, Shu-lin T, Hou-jun W, Cheng-lin Y (2013) Fault diagnosis of analog circuits based on Phasor circle model, vol 2. Proceedings of the IEEE 11th international conference on Electronic Measurement & Instruments, Harbin, pp 792–795

    Google Scholar 

  15. Zhihua L, Liuchang L (2016) Soft-fault diagnostic method based on locus circle of steady-state node-voltage vector. Int J Circuit Theory Appl 44(2):342–363

    Article  Google Scholar 

  16. Biernacki R, Bandler J (1981) Multiple-fault location of analog circuits. IEEE Trans Circuits Syst 28(5):361–367

    Article  Google Scholar 

  17. Lin C, Huang Z, Liu RW (1983) Topological conditions for single-branch-fault. IEEE Trans Circuits Syst 30(6):376–381

    Article  MathSciNet  Google Scholar 

  18. Starzyk J, Bandler J (1983) Multiport approach to multiple-fault location in analog circuits. IEEE Trans Circuits Syst 30(10):762–765

    Article  MathSciNet  Google Scholar 

  19. Peng M, He Y, Tan Y, Huang H, Sheng X (2003) Line fault location in a distribution network based on K-fault diagnosis method, vol 1. Proceedings of IEEE International Conference on Robotics, Intelligent Systems and Signal Processing, Hunan, pp 571–575

    Google Scholar 

  20. Huang JL, Cheng KT (2000) Test point selection for analog fault diagnosis of unpowered circuit boards. IEEE Trans Circuits Syst II: Analog Digital Signal Process 47(10):977–987

    Article  Google Scholar 

  21. Lin CS, Liu RW (1981) Fault directory approach-a case study. In: Proceedings IEEE International Symposium on Circuits and Systems, Chicago, p 239–242

  22. Djordjevic S (2018) Analog circuit diagnosis based on the nullor concept and multiport description of the circuit. Analog Integr Circ Sig Process 95(1):141–149

    Article  Google Scholar 

  23. Bandler J, Salama A (1985) Fault diagnosis of analog circuits. Proc IEEE 73(8):1279–1325

    Article  Google Scholar 

  24. Jiang BL, Wey CL, Fan LJ (1988) Fault prediction for analog circuits. J Circuits Syst Signal Process 7(1):95–109

    Article  MathSciNet  Google Scholar 

  25. Fedi G, Manetti S, Piccirilli M, Starzyk J (1999) Determination of an optimum set of testable components in the fault diagnosis of analog linear circuits. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 46(7):779–787

    Article  Google Scholar 

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Authors and Affiliations

  1. Faculty of Electronic Engineering, University of Nis, office 336, Aleksandra Medvedeva 14, Nis, 18000, Serbia

    Srdjan Djordjevic

  2. Faculty of Electronic Engineering, University of Nis, office 202, Aleksandra Medvedeva 14, Nis, 18000, Serbia

    Miroljub T. Pesic

Authors
  1. Srdjan Djordjevic
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  2. Miroljub T. Pesic
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Correspondence to Srdjan Djordjevic.

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Responsible Editor: M. Margala

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Djordjevic, S., Pesic, M.T. A Fault Verification Method Based on the Substitution Theorem and Voltage-Current Phase Relationship. J Electron Test 36, 617–629 (2020). https://doi.org/10.1007/s10836-020-05901-5

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  • DOI: https://doi.org/10.1007/s10836-020-05901-5

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