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Estimating Operational Age of an Integrated Circuit

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Abstract

Recycling of used ICs as new replacement parts in maintaining older electronic systems is a serious reliability concern. This paper presents a novel approach to estimate the operational age of CMOS chips by measuring IDDQ, the quiescent current from power supply or the total leakage current in steady state. This current decreases as the circuit ages, largely due to the increase in the magnitude of the PMOS transistor threshold voltage caused by negative bias temperature instability (NBTI). We exploit the fact that the impact of NBTI on an individual transistor depends upon the operational stress based upon the duration of its ON state. Novelty of our technique is a normalized difference, ΔI, computed from current measurements at two input test patterns and is proposed as a self referencing circuit age indicator. The first pattern is chosen such that its IDDQ is controlled by a large number of minimally stressed PMOS transistors; for the other the IDDQ is controlled by approximately equal number of highly stressed PMOS transistors. The difference between these two IDDQ values increases with the circuit age. This approach requires no hardware modification in the circuit and, hence, can be applied to legacy ICs. Simulation results show that we can reliably identify recycled ICs that have been used for as little as six months.

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Acknowledgments

This work was supported in parts by the National Science Foundation Grant CNS-1755733 and CCF-1527049.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, 75080, USA

    Prattay Chowdhury

  2. Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, 36849, USA

    Ujjwal Guin, Adit D. Singh & Vishwani D. Agrawal

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  1. Prattay Chowdhury
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Chowdhury, P., Guin, U., Singh, A.D. et al. Estimating Operational Age of an Integrated Circuit. J Electron Test 37, 25–40 (2021). https://doi.org/10.1007/s10836-021-05927-3

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