Abstract
A high-speed wireline interfaces, e.g. LVDS (Low Voltage Differential Signaling), are widely used in the aerospace field for powerful computing in artificial satellites and aircraft [19]. This paper describes Bit Error Rate (BER) prediction methodology for wireline data transmission under irradiation environment at the design stage of data transmitter, which is useful in proactively determining if the design circuit meets the BER criteria of the target system. Using a custom-designed LVDS transmitter (TX) to enhance latch-up immunity [42], the relationship between transistor size and BER has been analyzed with focusing on Single Event Effect (SEE) as a cause of the bit error. The measurement was executed under 84Kr17+ exposure of 322.0 MeV at various flux condition from 1 × 103 to 5 × 105 count/cm2/sec using cyclotron facility. For the analysis of the bit error, circuit simulation by SPICE was utilized with expressing the irradiation environment by a current source model. The current source model represents a single event strike into the circuit at drain and substrate junctions in bulk MOSFETs. For the construction of the current source model, a charge collection was simulated at the single particle strike with the creation of 3D Technology CAD (TCAD) models for the MOS devices of bulk transistor process technology. The simulation result of the charge correction was converted to a simple time-domain equation, and the single-event current source model was produced using the equation. The single-event current source was applied to SPICE simulation at bias current related circuits in the LVDS transmitter, then simulation results are carefully verified whether the output data is disturbed enough to cause bit errors on wireline data transmission. By the simulation, sensitive MOSFETs have been specified and a sum of the gate area for these MOSFETs has 29% better correlation than the normal evaluation index (sum of the drain area) by comparison to the actual BER measurement. Through the precise revelation of the sensitive area by SPICE simulation using the current model, it became possible to estimate BER under irradiation environment at the pre-fabrication design stage.
Similar content being viewed by others
Data Availability
Data of the BER measurement are available within this article. Simulation data that support the findings of this study are available, but restrictions apply to the availability of these data, which were used under license for this study. The data are available with the permission of Renesas Electronics Corporation from the corresponding author, Takefumi Yoshikawa, upon reasonable request.
References
Abhay M, Joshi (1998) Design of an integrated satellite (INT-SAT) using advanced semiconductor technology. In Proc. of American Institute of Physics (AIP) Conference 420:153–158
Boni A, Pierazzi A, Vecchi D (2001) LVDS I/O Interface for Gb/s-per-Pin Operation in 35um CMOS. IEEE J Solid-state circuits 36(4):706–711
Boulghassoul Y (2006) Towards SET Mitigation in RF Digital PLLs: From Error Characterization to Radiation Hardening Considerations. IEEE Trans Nucl Sci 53(4):2047–2053
Brady FT, Scott T, Brown R, Damato J, Haddad NF (1994) Fully-depleted submicron SOI for radiation hardened application. IEEE Trans Nucl Sci 41:2304–2308
Bryan MO et al (2003) Single event effects results for candidate spacecraft electronics for NASA. in Proc. IEEE Radiation Effects Data Workshop, Workshop Record, pp 65–75
Campola M, Pellish J (2019) Radiation hardness assurance: Evolving for new space. In Proc. of RADECS Short Course, Part V, Montpellier, France. 1–35
Chen Z, Dai FF (2011) A 3mW 8-bit radiation-hardened-by-design DAC for ultra-wide temperature range from −180 °C to 120 °C. In Proc of IEEE Int Symp Circuits Syst (ISCAS) 997–1000
Degalahal V, Li L, Narayanan V, Kandemir M, Irwin MJ (2005) Soft Errors Issues in Low-Power Caches. IEEE Trans on Very Large Scale Integration Sys 13(10):1157–1166
Detcheverry C, Dachs C, Lorfevre E, Sudre C, Bruguier G, Palau JM, Gasiot J, Ecoffet R (1997) SEU Critical Charge and Sensitive Area in a Submicron CMOS Technology. IEEE Transact Nuclear Sci 44(6):2266–2273
Dodd PE, Massengill LW (2003) Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans Nuc Sci 50(3)
Dupont E, Nicolaidis M, Rohr P (2002) Embedded Robustness IPs for Transient-Error-Free ICs. IEEE Des Test Comput 19(3):54–68
Ecoffet R (2013) Overview of In-Orbit Radiation Induced Spacecraft Anomalies. IEEE Trans Nucl Sci 60:1791–1815
IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface(SCI), 1596.3 SCI-LVDS Standard, IEEE Std. 1596.3–1996, March 1996.
England T, Chatterjee C, Lourenco N, Finn S, Najafizadeh L, Phillips S, Kenyon E, Diestelhorst R, Cressler J (2014) Cold-capable, radiation-hardened SiGeBiCMOS wireline transceivers. IEEE Aero Electron Syst Mag 29:32–41
Fibre Channel Physical Interface (2007) FC-PI 4 Standard ANSI INCITS/Project 1647-D/Rev7.00
Freeman LB (1996) Critical charge calculations for a bipolar SRAM array. IBM J Res Dev 40:119–129
Garg R, Khatri SP (2009) Analysis and design of resilient VLSI circuits mitigating soft errors and process variations. Springer, USA
Graceffa GA, Gatti U, Calligaro C (2016) A 400 Mbps Radiation Hardened By Design LVDS Compliant Driver and Receiver. In Proc. of 2016 IEEE Int Conf Electr Cir Sys (ICECS) 109–112
Hartwell M, Hafer C, Milliken P, Farris T (2005) Single event effects testing of a PLL and LVDS in a RadHard-by design 0.25-micron ASIC. In Proc. of IEEE NSREC 2005 Radiation Effects Data Workshop Record, pp 98–101
Hass KJ, Treece RK, Giddings AE (1989) A radiation-hardened 16/32-bit microprocessor. IEEE Trans Nucl Sci 36:2252–2257
Hazucha P, Svensson C (2000) Impact of CMOS technology scaling on the atmospheric neutron soft error rate. IEEE Trans Nucl Sci 47(6):2586–2594
Hazucha P, Svensson C, Wender SA (2000) Cosmic ray soft error rate characterization of a standard 0.6 um CMOS process. IEEE J Solid-State Circuits
Kim S, Tsuchiya A, Onodera H (2014) Radiation-hardened PLL with a switchable dual modular redundancy structure. IEICE Trans Electron E97-C(4):325–331
Kvålseth TO (1985) Cautionary Note about R2. Am Stat 39(4):279–285
Lantz L (1996) Soft Errors Induced by Alpha Particles. IEEE Trans. on Reliability 45(2)
Loveless T, Massengill L (2006) A Hardened-by-Design Technique for RF Digital Phase-Locked Loops. IEEE Trans Nucl Sci 53(6):3432–3438
Loveless TD, Massengill LW (2007) A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS. IEEE Trans Nucl Sci 54(6):2012–2020
Loveless TD, Massengill LW, Holman WT, Bhuva BL, Member S, Voltagecontrolled A (2007) Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators. IEEE Trans Nucl Sci 54(6):2561–2567
Loveless TD, Member S, Massengill LW, Bhuva BL, Member S, Holman WT, Casey MC, Reed RA, Nation SA, Mcmorrow D, Melinger JS (2008) A Probabilistic Analysis Technique Applied to a Radiation-Hardened-by-Design Voltage-Controlled Oscillator for Mixed-Signal Phase-Locked Loops. IEEE Trans Nucl Sci 55(6):3447–3455
Mandal G, Mandal P (2004) Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation. In Proc Int Symp Cir Sys 2004 ISCAS '04, 1120–1123
Massengill LW (1993) SEU modeling and prediction techniques. IEEE NSREC Short Course III-1-III-93
Matsuura D, Hirose K, Kobayashi D, Ishii S, Kusano M, Kuroda Y, Saito H (2011) Radiation-Hardened Phase-Locked Loop Fabricated in 200 nm SOI-CMOS. in European Conf on Radiation and Its Effects Comp Sys 150–155
May TC, Woods MH (1979) Alpha-particle-induced soft errors in dynamic memories. IEEE Trans Electron Devices 26:2–9
Mixcoatl FC, Jacome AT (2004) Latchup prevention by using guard ring structures in a 0.8um bulk CMOS process. Sperficies y Vacio 17–22
Naushad F, Dehriya S (2017) Testing methodology for fibre channel protocol in avionics applications. In Proc of 2017 Int Conf Recent Adv Electr Comm Technol (ICRAECT), Bangalore, pp 1–4
Pang T, Kang W, Ran Y, Zhang Y, Lv W, Zhao W (2015) Nonvolatile radiation hardened DICE latch. Proc of 2015 15th Non-Volatile Memory Technol Symp (NVMTS), Beijing 1–4
Streit DC, Gutierrez-Aitken A, Wojtowicz M, Lai R (2005) The future of compound semiconductors for aerospace and defense applications. In Proc. of Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC’05. IEEE 4
Sweeting MN (2018) Modern Small Satellites-Changing the Economics of Space. Proc of the IEEE 106(3):343–361
Tsai H-W, Ker M-D (2015) Improve latch-up immunity by circuit solution. In Proc of IEEE 22nd Int Symp Phys Failure Analysis of Integrated Circuits (IPFA) 527–230
Traversi G, De Canio F, Gaioni L, Manghisoni M, Ratti L, Re V, Bonacini S, Kloukinas K, Moreira P (2014) Design of low-power, low-voltage, differential I/O links for High Energy Physics applications. In Topical Workshop on Electr Par Phys TWEPP-14 22–26
Warren K, Stenberg A, Black J, Weller R, Reed R, Mendenhall M, Schrimpf R, Massengill L (2009) Heavy ion testing and single-event upset rate prediction considerations for a DICE flip-flop. IEEE Trans Nucl Sci 56(6):3130–3137
Yoshikawa T, Aoyama A, Iwata T, Kobayashi K (2019) LVDS Transmitter for Cold-Spare Systems in High Flux Environments. In Proc. of RADECS 2019, Oct. 2019 (to appear in IEEE Xplore)
Acknowledgements
This work was supported by TAKEUCHI MFG Research Grant. This work was also supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc., Synopsys, Inc., Mentor Graphics, Inc. and Renesas Electronics Corporation.
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
Conflicts of Interest
The authors have no conflicts of interest to declare that are relevant to the content of this article.
Additional information
Responsible Editor: H. Manhaeve
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Yoshikawa, T., Ishimaru, M., Iwata, T. et al. A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment. J Electron Test 37, 675–684 (2021). https://doi.org/10.1007/s10836-021-05972-y
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-021-05972-y