Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation

Abstract

Along with the advancement of technology, Negative bias temperature instability (NBTI) has now been considered a severe reliability threat in modern processors causing the device to deteriorate over time. SRAM-based architectures within the memory array are very much prone to the NBTI effect. Since SRAM cells are composed of cross-coupled inverters, one of the PMOS transistors will always be under constant stress and heavily degraded by NBTI, resulting in an increase in threshold voltage and degradation of SNM and performance of SRAM. Similarly, as one the PMOS transistor is always ON, so there will be a leakage power from $V_{DD}$ to the ground. In this paper, we have proposed a power gated SRAM architecture to reduce the NBTI effect and standby leakage power of a $4 \times 4$ SRAM array. The proposed gated logic is introduced during the hold state of the SRAM operation. So both the PMOS of the SRAM cell will be OFF during this period and will get sufficient time to relax from NBTI stress. The simulation result shows using our proposed approach overall, 30.41% NBTI-related $V_{th}$ degradation can be saved and considering only the standby mode, 96.24% NBTI-related degradation can be minimized compared to the conventional SRAM design. Moreover, 79.10% leakage power can be reduced over the conventional design using the proposed approach.