Skip to main content

Advertisement

Log in

FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Resistive memories have drawn the attention of researchers due to their low power and single-cycle computation of vector-matrix multiplication (VMM), which is the main operation performed in neural networks. For performing VMM, one of the most desirable architectures is the memristor crossbar that has several advantages over other memory technologies, viz. in-memory computation, low power, and high density. However, faults present in the crossbar can introduce errors in the inference process during neuromorphic computations. Existing methods to handle faults using retraining and remapping incur overheads in terms of hardware, power, and delay. In this paper we explore and analyze the impact of faults on memristor-based crossbar for overall inference accuracy. We have observed that the accuracy is not significantly affected in the presence of a limited number of faults. Also, the inference quality and effect of faults depend on the number of neural network layers and storage resolution of memristors present in the crossbar. The introduced approach works in three phases, fault tolerance analysis, high-level fault detection, and low-level fault detection. In the first phase, we analyze the fault tolerance capability of the crossbar, which identifies how many faults can be tolerated for a given application. In the second phase, we estimate the percentage of faults, and if it is below a threshold the third phase can be skipped. In the third phase, an efficient method to determine the exact location of the faults is used. The proposed method is capable of performing parallel operations, thus requiring fewer read/write steps as compared to existing works. The proposed approach requires O(N) read/write operations as compared to \(O(N^2)\) operations required in existing works.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

Data Availability Statement

This publication is supported by multiple datasets, which are openly available at locations cited in the reference section. Documentation for MNIST dataset is available at [22], and is openly available for download at http://yann.lecun.com/exdb/mnist/. Documentation for EMNIST dataset is available at [9], and is openly available for download at https://www.westernsydney.edu.au/icns/reproducible_research/publication_support_materials/emnist. Documentation for HAR dataset is available at [2], and is openly available for downloaded at https://archive.ics.uci.edu/ml/machine-learning-databases/00240/. Documentation of CIFAR-10 data is available at [19], and is openly available for downloaded at https://www.cs.toronto.edu/~kriz/cifar.html. Documentation of FMNIST is available at [37], and is openly available for download at https://github.com/zalandoresearch/fashion-mnist

References

  1. Akarvardar K, Wong HSP (2009) Ultralow voltage crossbar nonvolatile memory based on energy-reversible NEM switches. IEEE Electron Device Lett 30(6):626–628. https://doi.org/10.1109/LED.2009.2018289

    Article  Google Scholar 

  2. Anguita D, Ghio A, Oneto L, Parra X, Reyes-Ortiz JL, etal. (2013) A public domain dataset for human activity recognition using smartphones. In: Proc. 21th European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning ESANN 3

  3. Ankit A, Hajj IE, Chalamalasetti SR, Ndu G, Foltin M, Williams RS, Faraboschi P, Hwu WmW, Strachan JP, Roy K, Milojicic DS (2019) PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference. In: Proc. 24th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems 715-731. https://doi.org/10.1145/3297858.3304049

  4. Bushnell ML, Agrawal VD (2004) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. vol 17, Springer Science and Business Media, chap 4

  5. Chen CY, Shih HC, Wu CW, Lin CH, Chiu PF, Sheu SS, Chen FT (2015) Rram defect modeling and failure analysis based on march test and a novel squeeze-search scheme. IEEE Trans Comput 64(1):180–190. https://doi.org/10.1109/TC.2014.12

    Article  MathSciNet  MATH  Google Scholar 

  6. Chen L, Li J, Chen Y, Deng Q, Shen J, Liang X, Jiang L (2017) Accelerator-friendly neural-network training: Learning variations and defects in rram crossbar. In: Proc. Design, Automation Test in Europe Conference Exhibition (DATE)19-24. https://doi.org/10.23919/DATE.2017.7926952

  7. Chua LO (1971) Memristor-the missing circuit element. IEEE Transactions on Circuit Theory 18(5):507–519. https://doi.org/10.1109/TCT.1971.1083337

    Article  Google Scholar 

  8. Chua LO, Sung MK (1976) Memristive devices and systems. Proc IEEE 64(2):209–223. https://doi.org/10.1109/PROC.1976.10092

    Article  MathSciNet  Google Scholar 

  9. Cohen G, Afshar S, Tapson J, van Schaik A (2017) EMNIST: Extending MNIST to handwritten letters. In: Proc. International Joint Conference on Neural Networks (IJCNN) IEEE 2921–2926. https://doi.org/10.1109/IJCNN.2017.7966217

  10. Danaboina YKY, Samanta P, Datta K, Chakrabarti I, Sengupta I (2019) Design and implementation of threshold logic functions using memristors. In: Proc. 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID) 518–519. https://doi.org/10.1109/VLSID.2019.00115

  11. Dua D, Graff C (2017) UCI machine learning repository. http://archive.ics.uci.edu/ml

  12. Gu P, Li B, Tang T, Yu S, Cao Y, Wang Y, Yang H (2015) Technological exploration of rram crossbar array for matrix-vector multiplication. In: Proc. The 20th Asia and South Pacific Design Automation Conference 106–111. https://doi.org/10.1109/ASPDAC.2015.7058989

  13. Hongal VA, Kotikalapudi R, Kim YB, Choi M (2011) A novel “divide and conquer” testing technique for memristor based lookup table. In: Proc. IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) 1-4. https://doi.org/10.1109/MWSCAS.2011.6026406

  14. Hossam H, Mamdouh G, Hussein H, El-Dessouky M, Mostafa H (2018) A new read circuit for multi-bit memristor-based memories based on time to digital sensing circuit. In: Proc. IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) 1114–1117. https://doi.org/10.1109/MWSCAS.2018.8623907

  15. Hu M, Graves CE, Li C, Li Y, Ge N, Montgomery E, Davila N, Jiang H, Williams RS, Yang JJ, Xia Q, Strachan JP (2018) Memristor-based analog computation and neural network classification with a dot product engine. Adv Mater 30(9):1705914. https://doi.org/10.1002/adma.201705914

    Article  Google Scholar 

  16. Huangfu W, Xia L, Cheng M, Yin X, Tang T, Li B, Chakrabarty K, Xie Y, Wang Y, Yang H (2017) Computation-oriented fault-tolerance schemes for rram computing systems. In: Proc. 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) 794–799. https://doi.org/10.1109/ASPDAC.2017.7858421

  17. Kannan S, Rajendran J, Karri R, Sinanoglu O (2013) Sneak-path testing of memristor-based memories. In: Proc. 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems. 386–391. https://doi.org/10.1109/VLSID.2013.219

  18. Kannan S, Karimi N, Karri R, Sinanoglu O (2015) Modeling, detection, and diagnosis of faults in multilevel memristor memories. IEEE Trans Comput Aided Des Integr Circuits Syst 34(5):822–834. https://doi.org/10.1109/TCAD.2015.2394434

    Article  Google Scholar 

  19. Krizhevsky A, Nair V, Hinton G (2009) Cifar-10 (canadian institute for advanced research) 5:4. http://www.cs.toronto.edu/kriz/cifar.html

  20. Kvatinsky S, Belousov D, Liman S, Satat G, Wald N, Friedman EG, Kolodny A, Weiser UC (2014) Magic–memristor-aided logic. IEEE Transactions on Circuits and Systems II: Express Briefs 61(11):895–899. https://doi.org/10.1109/TCSII.2014.2357292

  21. Kvatinsky S, Ramadan M, Friedman EG, Kolodny A (2015) VTEAM: A general model for voltage-controlled memristors. IEEE Trans Circuits Syst II Express Briefs 62(8):786–790. https://doi.org/10.1109/TCSII.2015.2433536

    Article  Google Scholar 

  22. LeCun Y (1998) The mnist database of handwritten digits. http://yann.lecun.com/exdb/mnist/

  23. Liu B, Li H, Chen Y, Li X, Wu Q, Huang T (2015) Vortex: Variation-aware training for memristor x-bar. In: Proc. 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) 1–6. https://doi.org/10.1145/2744769.2744930

  24. Liu M, Xia L, Wang Y, Chakrabarty K (2019) Fault tolerance in neuromorphic computing systems. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference 216-223 https://doi.org/10.1145/3287624.3288743

  25. Merced-Grafals EJ, Dávila N, Ge N, Williams RS, Strachan JP (2016) Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications. Nanotechnology 27(36):365202. https://doi.org/10.1088/0957-4484/27/36/365202

  26. Reuben J, Fey D, Wenger C (2019) A modeling methodology for resistive RAM based on Stanford-PKU model with extended multilevel capability. IEEE Trans Nanotechnol 18:647–656. https://doi.org/10.1109/TNANO.2019.2922838

    Article  Google Scholar 

  27. Shafiee A, Nag A, Muralimanohar N, Balasubramonian R, Strachan JP, Hu M, Williams RS, Srikumar V (2016) Isaac: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In: Proc. ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) 14–26. https://doi.org/10.1109/ISCA.2016.12

  28. Sheridan PM, Cai F, Du C, Ma W, Zhang Z, Lu WD (2017) Sparse coding with memristor networks. Nat Nanotech (12):784-789. https://doi.org/10.1038/nnano.2017.83

  29. Song L, Qian X, Li H, Chen Y (2017) Pipelayer: A pipelined ReRAM-based accelerator for deep learning. In: Proc. IEEE International Symposium on High Performance Computer Architecture (HPCA) 541–552 https://doi.org/10.1109/HPCA.2017.55

  30. Strukov DB, Snider GS, Stewart DR, Williams RS (2008) The missing memristor found. Nature 453(7191):80–83. https://doi.org/10.1038/nature06932

    Article  Google Scholar 

  31. Taherinejad N, Manoj PS, Jantsch A (2015) Memristors’ potential for multi-bit storage and pattern learning. In: Proc. IEEE European Modelling Symposium (EMS) 450–455. https://doi.org/10.1109/EMS.2015.73

  32. Tam S, Gupta B, Castro H, Holler M (1990) Learning on an analog VLSI neural network chip. In: Proc. IEEE International Conference on Systems, Man, and Cybernetics Conference Proceedings 701–703. https://doi.org/10.1109/ICSMC.1990.142209

  33. Thangkhiew PL, Gharpinde R, Datta K (2018) Efficient mapping of boolean functions to memristor crossbar using magic nor gates. IEEE Trans Circuits Syst I Regul Pap 65(99):2466–2476. https://doi.org/10.1109/TCSI.2018.2792474

    Article  MathSciNet  MATH  Google Scholar 

  34. Xia L, Gu P, Li B, Tang T, Yin X, Huangfu W, Yu S, Cao Y, Wang Y, Yang H (2016) Technological exploration of RRAM crossbar array for matrix-vector multiplication. J Comput Sci Technol 31(1):3–19. https://doi.org/10.1007/s11390-016-1608-8

    Article  MathSciNet  Google Scholar 

  35. Xia L, Liu M, Ning X, Chakrabarty K, Wang Y (2017) Fault-tolerant training with on-line fault detection for RRAM-based neural computing systems. In: Proc. 54th ACM/EDAC/IEEE Design Automation Conference (DAC) 1–6. https://doi.org/10.1145/3061639.3062248

  36. Xia L, Huangfu W, Tang T, Yin X, Chakrabarty K, Xie Y, Wang Y, Yang H (2018) Stuck-at fault tolerance in RRAM computing systems. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8(1):102–115. https://doi.org/10.1109/JETCAS.2017.2776980

    Article  Google Scholar 

  37. Xiao H, Rasul K, Vollgraf R (2017) Fashion-mnist: a novel image dataset for benchmarking machine learning algorithms http://arxiv.org/abs/1708.07747

  38. Xu Q, Chen S, Geng H, Yuan B, Yu B, Wu F, Huang Z (2020) Fault tolerance in memristive crossbar-based neuromorphic computing systems. Integration 70:70–79. https://doi.org/10.1016/j.vlsi.2019.09.008

    Article  Google Scholar 

  39. Yadav DN, Thangkhiew PL, Datta K (2019) Look-ahead mapping of boolean functions in memristive crossbar array. Integration 64:152–162. https://doi.org/10.1016/j.vlsi.2018.10.001

    Article  Google Scholar 

  40. Yadav DN, Datta K, Sengupta I (2020) Analyzing fault tolerance behaviour in memristor-based crossbar for neuromorphic applications. In: 2020 IEEE International Test Conference India 1–9 https://doi.org/10.1109/ITCIndia49857.2020.9171788

  41. Yang JJ, Strukov DB, Stewart DR (2013) Memristive devices for computing. Nature nanotechnology 8(1):13. https://doi.org/10.1038/nnano.2012.240

    Article  Google Scholar 

  42. Zhang B, Uysal N, Fan D, Ewetz R (2020a) Handling stuck-at-fault defects using matrix transformation for robust inference of dnns. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39(10):2448–2460. https://doi.org/10.1109/TCAD.2019.2944582

  43. Zhang B, Uysal N, Fan D, Ewetz R (2020b) Redundant neurons and shared redundant synapses for robust memristor-based DNNs with reduced overhead. In: Proceedings of the ACM Great Lakes Symposium on VLSI 339-344. https://doi.org/10.1145/3386263.3406910

Download references

Author information

Authors and Affiliations

Authors

Contributions

All authors have equally contributed in the study and writing of this manuscript. The manuscript has been read and approved for submission by all authors

Corresponding author

Correspondence to Dev Narayan Yadav.

Ethics declarations

Ethical Approval

Not applicable.

Consent to Participate

Not applicable.

Conflicts of Interest

The authors declare no conflict of interest.

Additional information

Responsible editor:  L. M. Bolzani Poehls

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yadav, D.N., Thangkhiew, P.L., Datta, K. et al. FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications. J Electron Test 38, 145–163 (2022). https://doi.org/10.1007/s10836-022-06001-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-022-06001-2

Keywords

Navigation