Skip to main content
Springer Nature Link
Log in

Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Hardware security has become most prevalent challenging concept of improving the Internet of Things (IoT) in human routine as well as in future engineering processes. IoT systems face a wide range of problems, including a dearth of resources, a requirement for equipment protection from cyber-attacks, and lower power consumption. Especially, the methods are constrained by power consumption and an insufficient of computing capacity. Moreover, the customary method of keeping secret keys in non-volatile memory is susceptible to assaults like side-channelling and reverse engineering. Physical Unclonable Functions (PUFs) are a technique for improving security of physical device and resolving difficulties with current cryptographic algorithms. PUFs are simple operations that force each terminal to have a unique personality based on physical characteristics imposed during production that are unpredictable and impossible to replicate. The focus of this work is on XOR arbiter PUF (XORAPUF) architecture with the three factors: reliability, uniqueness, and uniformity. Experiments show that the proposed XORAPUF implemented on field programmable gate array (FPGA) achieves inter-chip hamming distance (HD) closer to 50% with excellent uniqueness and uniformity of 49.88% and 48.74%, respectively. The reliability of the designed PUF is also optimized to 99.20%. On comparing the designed PUF metrics results with conventional PUF, the XORAPUF circuit generated better results.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

Data Availability

Not Applicable.

References

  1. El-hajj M, Chamoun M, Fadlallah A, Serhrouchni A (2017) Taxonomy of authentication techniques in Internet of Things (IoT). IEEE 15th Student Conference on Research and Development (SCOReD) 67–71. https://doi.org/10.1109/SCORED.2017.8305419

  2. El-hajj M, Fadlallah A, Chamoun M, Serhrouchni A (2019) A Survey of Internet of Things (IoT) Authentication Schemes. Sensors (Basel, Switzerland) 19(5):1141. https://doi.org/10.3390/s19051141

    Article  Google Scholar 

  3. Naveenkumar R, Sivamangai N M, Napolean A, Janani V (2021) A Survey on Recent Detection Methods of the Hardware Trojans. 3rd International Conference on Signal Processing and Communication (ICPSC) 139–143. https://doi.org/10.1109/ICSPC51351.2021.9451682

  4. Naveenkumar R, Sivamangai N M, Napolean A, Nissi G A (2022) Hardware Obfuscation for IP Protection of DSP Applications. J. Electron. Test 38: 9–20. https://doi.org/10.1007/s10836-022-05984-2

  5. Sahoo DP, Chakraborty RS, Mukhopadhyay D (2015) Towards Ideal Arbiter PUF Design on Xilinx FPGA: A Practitioner’s Perspective. Euromicro Conference on Digital System Design. https://doi.org/10.1109/dsd.2015.51

    Article  Google Scholar 

  6. Mahalat M H, Mandal S, Mondal A, Sen B (2019) An Efficient Implementation of Arbiter PUF on FPGA for IoT Application. 32nd IEEE International System-on-Chip Conference (SOCC) 324–329. https://doi.org/10.1109/socc46988.2019.157054

  7. Gope P, Lee J, Quek TQ (2018) Lightweight and Practical Anonymous Authentication Protocol for RFID Systems Using Physically Unclonable Functions. IEEE Trans Inf Forensics Secur 13:2831–2843. https://doi.org/10.1109/TIFS.2018.2832849

    Article  Google Scholar 

  8. He Z, Chen W, Zhang L, Chi G, Gao Q, Harn L (2020) A Highly Reliable Arbiter PUF With Improved Uniqueness in FPGA Implementation Using Bit-Self-Test. IEEE Access 8:181751–181762. https://doi.org/10.1109/access.2020.3028514

    Article  Google Scholar 

  9. Zalivaka SS, Ivaniuk AA, Chang C (2017) Low-cost fortification of arbiter PUF against modeling attack. IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/iscas.2017.8050671

    Article  Google Scholar 

  10. Tajik S, Dietz E, Frohmann S, Seifert J, Nedospasov D, Helfmeier C, Boit C, Dittrich H (2014) Physical Characterization of Arbiter PUFs. IACR Cryptol ePrint Arch. https://doi.org/10.1007/978-3-662-44709-3_27

    Article  MATH  Google Scholar 

  11. Lim D, Lee J W, Gassend B, Suh G E, Dijk M V, Devadas S (2005) Extracting secret keys from integrated circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13:1200–1205. https://doi.org/10.1109/TVLSI.2005.859470

  12. Yao J, Pang L, Zhang Z, Yang W, Fu A, Gao Y (2022) Design and Evaluate Recomposited OR-AND-XOR-PUF. IEEE Trans. Emerg. Top. Comput. 10: 662–677. https://doi.org/10.1109/tetc.2022.3170320

  13. Gu C, Liu W, Cui Y, Hanley N, O’Neill M, Lombardi F (2021) A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation. IEEE Trans Emerg Top Comput 9(4):1853–1866. https://doi.org/10.1109/TETC.2019.2935465

    Article  Google Scholar 

  14. Hospodar G, Maes R, Verbauwhede I M (2012) Machine learning attacks on 65nm Arbiter PUFs: Accurate modeling poses strict bounds on usability. 2012 IEEE International Workshop on Information Forensics and Security (WIFS) 37–42. https://doi.org/10.1109/WIFS.2012.6412622

  15. Alkatheiri MS, Zhuang Y (2017) Towards fast and accurate machine learning attacks of feed-forward arbiter PUFs. IEEE Conference on Dependable and Secure Computing. https://doi.org/10.1109/DESEC.2017.8073845

    Article  Google Scholar 

  16. Mursi KT, Thapaliya B, Zhuang Y, Aseeri AO, Alkatheiri MS (2020) A Fast Deep Learning Method for Security Vulnerability Study of XOR PUFs. Electronics 9(10):1715. https://doi.org/10.3390/electronics9101715

    Article  Google Scholar 

  17. Lin L, Holcomb DE, Krishnappa DK, Shabadi P, Burleson WP (2010) Low-power sub-threshold design of secure physical unclonable functions. ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED). https://doi.org/10.1145/1840845.1840855

    Article  Google Scholar 

  18. Machida T, Yamamoto D, Iwamoto M, Sakiyama K (2015) Implementation of double arbiter PUF and its performance evaluation on FPGA. The 20th Asia and South Pacific Design Automation Conference 6–7. https://doi.org/10.1109/ASPDAC.2015.7058919

  19. Zalivaka SS, Ivaniuk AA, Chang C (2019) Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response. IEEE Trans Inf Forensics Secur 14:1109–1123. https://doi.org/10.1109/tifs.2018.2870835

    Article  Google Scholar 

  20. Patterson M, Zambreno J, Sabotta C, Vyas S, Mills A (2011) Ring Oscillator PUF Design and Results

  21. Wen J, Huang M, Chen Z, Zhu L, Chen S, Li B (2019) A Multi-line Arbiter PUF with Improved Reliability and Uniqueness. IEEE 4th International Conference on Signal and Image Processing (ICSIP) 641–648. https://doi.org/10.1109/siprocess.2019.886888

  22. Ge W, Hu S, Huang J, Liu B, Zhu M (2020) FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance. IEICE Electron Express 17(2):1–6. https://doi.org/10.1587/elex.16.20190670

    Article  Google Scholar 

  23. Ruhrmair U, Sehnke F, Solter, J, Dror G, Devadas S, Schmidhuber J (2010) Modeling attacks on physical unclonable functions. Proceedings of the 17th ACM conference on Computer and communications security 237–249. https://doi.org/10.1145/1866307.1866335

  24. Mursi K T, Zhuang Y, Alkatheiri M S, Aseeri A O (2019) Extensive Examination of XOR Arbiter PUFs as Security Primitives for Resource-Constrained IoT Devices. 17th International Conference on Privacy, Security and Trust (PST) 1–9. https://doi.org/10.1109/pst47121.2019.8949070

  25. Aseeri AO, Zhuang Y, Alkatheiri MS (2018) A Machine Learning-Based Security Vulnerability Study on XOR PUFs for Resource-Constraint Internet of Things. IEEE International Congress on Internet of Things (ICIOT). https://doi.org/10.1109/ICIOT.2018.00014

    Article  Google Scholar 

  26. Becker G T (2015) The Gap Between Promise and Reality: On the Insecurity of XOR Arbiter PUFs. Cryptographic Hardware and Embedded Systems (CHES), Lecture Notes in Computer Science (9293):535–555. https://doi.org/10.1007/978-3-662-48324-4_27

  27. Majzoobi M, Rostami M, Koushanfar F, Wallach DS, Devadas S (2012) Slender PUF Protocol: A Lightweight, Robust, and Secure Authentication by Substring Matching. IEEE Symposium on Security and Privacy Workshops. https://doi.org/10.1109/SPW.2012.30

    Article  Google Scholar 

  28. Ruhrmair U, Solter J, Sehnke F, Xu X, Mahmoud A, Stoyanova V, Dror G, Schmidhuber J, Burleson WP, Devadas S (2013) PUF Modeling Attacks on Simulated and Silicon Data. IEEE Trans Inf Forensics Secur 8(11):1876–1891. https://doi.org/10.1109/TIFS.2013.2279798

    Article  Google Scholar 

  29. Sushma R, Murty N S (2018) Feedback Oriented XORed Flip-Flop Based Arbiter PUF. International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) 1444–1448. https://doi.org/10.1109/iceeccot43722.2018.9001605

Download references

Author information

Authors and Affiliations

  1. Research Scholar, Dept. of ECE, Karunya Institute of Technology and Sciences, Tamilnadu, Coimbatore, 641114, India

    R. Naveenkumar & A. Napolean

  2. Dept. of ECE, Karunya Institute of Technology and Sciences, Tamilnadu, Coimbatore, 641114, India

    N. M. Sivamangai & S. Sridevi Sathya Priya

Authors
  1. R. Naveenkumar
    View author publications

    You can also search for this author inPubMed Google Scholar

  2. N. M. Sivamangai
    View author publications

    You can also search for this author inPubMed Google Scholar

  3. A. Napolean
    View author publications

    You can also search for this author inPubMed Google Scholar

  4. S. Sridevi Sathya Priya
    View author publications

    You can also search for this author inPubMed Google Scholar

Contributions

The first author wrote the manuscript, and the second author supervised, third and fourth author- done the proof reading.

Corresponding author

Correspondence to R. Naveenkumar.

Ethics declarations

Research Involving Human and Animal Participants

Not Applicable.

Competing Interests

Nil.

Additional information

Responsible Editor: S. Bhunia

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Naveenkumar, R., Sivamangai, N.M., Napolean, A. et al. Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications. J Electron Test 38, 653–666 (2022). https://doi.org/10.1007/s10836-022-06034-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-022-06034-7

Keywords