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Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit

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Abstract

Single Event Transients (SET) pose a growing challenge to reliability of memory circuits as the device dimensions continue to shrink. It is essential to assess the effect of decreasing technology lengths on the resilience and power dissipation of the circuit. This paper proposes Dual Interlocked Storage Cell (DICE) based Radiation Hardened by Design (RHBD) Static Random Access Memory (SRAM) circuit design with appropriate sizing ratios for 180 nm, 90 nm and 45 nm channel lengths. The effect of variation in voltage in these technology nodes is analysed by a comparison of power dissipation calculated through simulations on Cadence. For an input voltage of 1.1 V, the power dissipation is calculated as 0.175nW for 180 nm technology length, 0.086nW for 90 nm technology length and 0.018nW for 45 nm technology length. It shows that the power dissipation gets almost halved when the technology switch is made from 180 nm to 90 nm and the power dissipation decrease is almost ten times from 180 nm to 45 nm technology. Mobility and doping parameters are found to be varying with device dimensions and the magnitude of that variation is studied. The parameters are related with the vulnerability to SET and affect the circuit’s resilience to radiation.

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Authors and Affiliations

  1. Department of ECE, Punjab Engineering College (Deemed to be University), Chandigarh, India

    Neha Pannu, Neelam Rup Prakash & Jasbir Kaur

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  1. Neha Pannu
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  2. Neelam Rup Prakash
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  3. Jasbir Kaur
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Correspondence to Neha Pannu.

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Pannu, N., Prakash, N.R. & Kaur, J. Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit. J Electron Test 38, 579–587 (2022). https://doi.org/10.1007/s10836-022-06036-5

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