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A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing

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Abstract

Higher complexity in recent chip designs, module integration, and increasing test quality requirements have expanded measurement needs and further increased chip test costs. Multi-site testing (parallel measurement) solves this issue by taking test measurements from multiple chips simultaneously, massively increasing throughput, and significantly reducing the test time per chip. Massive multi-site testing system, a setup with significant measurement site count, further improves throughput and maximizes gains. However, it unavoidably amplifies site-to-site variations in the measured specifications. This problem is particularly magnified in analog and mixed-signal chips. Some measurement sites now exhibit pronounced induced errors, and their measurements no longer reflect the actual performance of the device under test (DUT). This problem presents a solid need to identify sites that suffer from extreme site-to-site variations (issue sites). We propose an automated method to investigate site-to-site variations in volume multi-site data and identify issue sites that may not be obvious via human inspection or basic statistical methods. Assuming that all measurement sites have the same accuracy and precision, we consider an issue site to be one whose weighted-bin difference score is greater than an analytically derived upper bound. We apply the proposed method to simulation data and volume test data obtained from an industrial analog and mixed-signal system on chips (SoCs) that were tested using multi-site testing hardware and show that the technique can effectively identify issue sites in the testing system. We compare the proposed algorithm to existing methods and demonstrate its superior performance.

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Data Availability

The data that support the findings of this study are available from Texas Instruments Inc, but restrictions apply to the availability of these data, which were used under license for the current study, and so are not publicly available. Data are however, available from the authors upon reasonable request and with permission of Texas Instruments Inc.

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Acknowledgments

This work was supported in part by Texas Instruments and in part by the Semiconductor Research Corporation.

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Authors and Affiliations

  1. Iowa State University of Science and Technology, Iowa State University, Ames, IA, USA

    Isaac Bruce, Praise O. Farayola, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi & Degang Chen

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  1. Isaac Bruce
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Correspondence to Isaac Bruce.

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Bruce, I., Farayola, P.O., Chaganti, S.K. et al. A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing. J Electron Test 39, 57–69 (2023). https://doi.org/10.1007/s10836-023-06047-w

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