1 Introduction

This paper quantifies the process of wafer fabrication and testing assuming that the characteristics of wafer products are normally distributed and applies the digital integrated circuit test model (DITM) [1,2,3,4] to estimate the test yield (Yt) and quality of integrated circuit (IC) products. The rate of progress in future manufacturing is unpredictable. Therefore, we use current manufacturing techniques and the electrical characteristics of existing products to estimate the distribution trend of future product yields.

The ultimate goal of semiconductor manufacturing is to produce zero-defect [5,6,7,8,9] and high-quality IC products. In particular, the automotive electronics industry, which has high safety requirements, has extremely strict quality requirements. A key indicator of general semiconductor quality uses defects per million to express the failure rate of semiconductor components. However, the defect metric was changed from parts per million (PPM) to parts per billion for some critical parts. Improving the quality of products can reduce abnormal electronic components and improve driving safety. Most current test methods fail to meet the yield and quality needs of the automotive electronics market; thus, suppliers must reevaluate their test plans to find additional cost-effective alternatives to current test methods [10,11,12,13,14,15,16,17,18,19]. For example, Teslence Technology Co. Ltd. developed a new test method [10] and applied it to the test production line of ASE Technology Holding Co. Ltd., the world’s largest wafer test factory, to improve the test yield (Yt) of chip products. In addition, the American Automotive Electronics Council (AEC) established the AEC-Q001 [7] specification, which uses the part average testing method to eliminate problematic parts, increase product reliability, and improve the quality of components.

The testing capability has failed to compete with the process capability; thus, if no breakthrough development in the testing method of the chips emerges in the future, then the test yield (Yt) will be increasingly worse due to the inaccuracy of the VLSI tester [20,21,22]. To solve this problem, we propose an effective multiple retest system (MRS) that utilizes moving guardband testing to improve test yield (Yt) and test quality (DL, defect level), thus realizing the high-quality zero-defect goals required for avionics and biomedical electronics through cost estimation and effective retesting.

We use data from the 2021 International Roadmap for Devices and Systems (IRDS) [23] table and the DITM model to estimate future yield trends and apply the test–retest method to chip testing (zero defect) with strict quality requirements (biomedical and automotive electronics). Under the feedback of cost calculation, the occurrence of killing errors (α) and missing errors (β) is minimized to reduce unnecessary waste production and decrease testing costs. The improvement of the test yield (Yt) increases the number of sold chips, which not only improves the chip sale profits of the company but also allows the selling of additional high-quality chips. Therefore, a shortage of materials in the electronics industry has been encountered considering the impact of global semiconductors caused by the COVID-19 epidemic. The retest method not only improves the performance of semiconductor test equipment but also enhances the test yield (Yt) and increases the global supply of semiconductor chips.

2 Manufacturing and Testing Errors of Semiconductor Wafers

The development sequence of an IC is changed from a design concept in the design house to circuit design. Wafer fabrication is then conducted at the wafer foundry and the IC is finally sent to the test house for analysis (Fig. 1). Chemical concentration, etching, and mask errors [20, 21] in the wafer foundry manufacturing process result in the loss of manufacturing yield (Ym). In addition to environmental factors in the foundry manufacturing process, tester accuracy, and test methods during test house testing can affect yield and quality.

Fig. 1
figure 1

Process and test errors in the IC manufacturing process

In the process of IC development and manufacturing (Fig. 2), assuming that we have manufactured N number of chips, the chips can be divided into good and bad parts according to the formulation parameters of the design specification (DS). The manufacturing yield (Ym) after chip foundry manufacturing can be expressed as Ym = G/N. This yield is then sent to the testing house for analysis. The test specifications (TS) provided by the manufacturer can be divided into two types: pass (P) and failure (F) parameters. If the testing process is perfect, then the ATE tester can classify products into good and bad, which respectively pass and fail the test. In this case, the test yield (Yt) and the manufacturing yield (Ym) will be the same. Test errors are caused by instrument errors or measurement uncertainty, causing killing errors (α) and missing errors (β). Missing errors (the number of bad chips that pass the test) can lead to product returns and affect the image of the company. Killing errors (the number of good chips that fail tests) increase product cost and yield loss and reduce corporate revenue margins.

Fig. 2
figure 2

Test flow and errors for semiconductor ICs

2.1 Calculation of Chip Manufacturing Yield (ym)

In general traditional statistical analysis, the normal distribution is a theoretical pattern and distribution type that is often used because of its accuracy. Let N (x; μ, σ) denote the probability density function of a normal distribution for a random variable X with mean μ and standard deviation σ. The probability density function of the normal distribution is expressed as

$$\mathrm{f}\left(\mathrm{x}\right)=\frac{1}{\sqrt{2\uppi }\upsigma }{\mathrm{e}}^{-\frac{1}{2}{\left(\frac{\mathrm{X}-\upmu }{\upsigma }\right)}^{2}}\mathrm{dx}$$
(1)

After hundreds of semiconductor manufacturing procedures, the chip delay time has a probability distribution rather than a fixed value due to uncertain changes in the process. Herein, we assume that the delay time of the device under test (DUT) is normal, that is, Chip (x) = N (x; μM, σM), mean μM and standard deviation σM. The Ym (manufacturing Yield) is the probability of the area under the normal curve between the coordinates x = − ∞ and x = DS, that is, P[− ∞ < X < DS]. We find

$$\begin{aligned}{\mathrm{Y}}_{\mathrm{m}}&=\mathrm{Manufacturing\ Yield}\\& =\int_{-\infty}^{\mathrm{DS}}\mathrm{Chip}\left(\mathrm{x}\right)\mathrm{dx}\\& =\int_{-\infty}^{\mathrm{DS}}\frac{1}{{\sqrt{2\uppi}\upsigma }_{\mathrm{M}}}{\mathrm{e}}^{-\frac{1}{2}{\left(\frac{\mathrm{X}-{\upmu}_{\mathrm{M}}}{{\sigma}_{\mathrm{M}}}\right)}^{2}}\mathrm{ dx}\\& =\int_{-\infty }^{\frac{DS-{\mu }_{M}}{{\upsigma}_{M}}}\frac{1}{\sqrt{2\pi }}{\mathrm{e}}^{-\frac{1}{2}{\left(x\right)}^{2}}\mathrm{dx}.\end{aligned}$$
(2)

Taking the chip circuit as an example, the design house establishes a CPU (central processing unit) with a DS of 0.858 GHz (DS = 1165 ps) and electrical characteristics, including mean μM = 1000 ps (picoseconds) and standard deviation σM = 100 ps. The chip delay time distribution can be represented by chip X ~ N (x; μM = 1000 ps and σM = 100 ps). Figure 3 shows the normal distribution of the chip delay time. The horizontal and vertical axes represent the time parameter of circuit characteristics and the probability density of time, respectively. According to the calculation of formula (2), 95% manufacturing yield (true yield) can be obtained Ym = P[Good] = P[X < DS] = 95%.

Fig. 3
figure 3

Manufacturing yield (Ym) distribution and estimation

2.2 Chip Testing Yield (yt) Estimation

IC testing contains many projects, including delay testing, parameter testing, and function testing. Additionally, three general categories of defect classes are as follows: (A) bridge, (B) open circuit, and (C) parametric defects. Even between wafers of the same process, there are differences due to process capability. Therefore, the test circuit (Test Key) is often used for testing on the wafer. However, because the chip contains too many parameters, the parameter relationship between each layer is complicated. Although we know that the best test circuit for the chip is itself, the current application test circuit is mainly to monitor the process. Therefore, it is very useful to test the parameters of the circuit to judge whether the chip is good or bad. In general, using key parameters to determine whether a chip is good or bad will not only affect the test cost and speed, but also the final test results. As a result, we refer to the test parameters of chip products and electrical appliances, as well as consider the speed of progress in process capabilities and the development of automated test equipment (ATE) capabilities. Finally, we employed the timing speed parameters of ATE and the delay time parameters of the chip to judge the quality of its wafer products to simplify the calculation of wafer test yield and quality. Figure 4 shows the threshold test system, wherein the signal sent by the IC tester (ATE) is compared with the delayed signal in the ATE. In the tester system model, X1 is the expected chip delay time of the DUT, and X2 (strobe) is the test strobe time as measured by the tester. The two signals are sent to the comparator of the IC tester, which compares the fast, and slow timing to determine whether the chip product is good or bad. Based on the output of the timing comparator, the D-type flip-flop judges the pass and fail of the product. ATE can determine whether the DUT is a “pass” or “fail” chip based on the timing comparison of the two signals. Vref provides an input fixed reference voltage to the comparator, If × 1 > Vref, then V0 = Vcc; if × 1 < Vref, then V0 = 0. If the tester signal arrives faster than the chip delay time (X1 > X2), the chip is classified as faulty, and a fault is signaled. Conversely, if the tester signal is slower than the chip delay time (X1 < X2), then the chip is classified as a good part, and the test passes.

Fig. 4
figure 4

IC Testing Model

Chips after fabrication may produce chips that meet specifications and those that do not meet specifications due to uncertain factors in the semiconductor manufacturing process. We can select the bad chips by using the testing mechanism through the testing steps. However, the signal ST sent out by the ATE tester demonstrates edge displacement due to the inaccuracy of the IC tester (ATE). Therefore, we assume that the performance of the test equipment (tester) is normally distributed in this study. The electrical distribution of the test equipment is X ~ N (x; μT, σT), (tester) mean μT, and standard deviation σT. After estimation, the test yield Yt is calculated as Yt = P[pass] = P[X < Y] and can be expressed as the following:

$$\begin{aligned}\mathrm{Test\ Yield}&=\;{\mathrm{Y}}_{\mathrm{t}} \left(\mathrm{\%}\right)\\& =\mathrm{ P}\left[\mathrm{pass}\right]=\mathrm{ P}\left[\mathrm{x }<\mathrm{ y}\right]\\& =\int_{-\infty }^{\infty }\mathrm{Chip}\left(\mathrm{x}\right)\int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{y}, {\upmu }_{\mathrm{T}}\right)\mathrm{dydx}\\& =\int_{-\infty }^{\infty }\frac{1}{{\sqrt{2\uppi }\upsigma }_{\mathrm{M}}}{\mathrm{e}}^{-\frac{1}{2}{\left(\frac{\mathrm{X}-{\upmu }_{\mathrm{M}}}{{\upsigma }_{\mathrm{M}}}\right)}^{2}}\underset{\mathrm{x}}{\overset{\infty }\int}\frac{1}{{\sqrt{2\uppi }\upsigma }_{\mathrm{T}}}{\mathrm{e}}^{{-\frac{1}{2}\left(\frac{\mathrm{y}-{\upmu }_{\mathrm{T}}}{{\upsigma }_{\mathrm{T}}}\right)}^{2}}\mathrm{dydx}\\&=\int_{-\infty }^{\infty }\frac{1}{\sqrt{2\uppi }}{\mathrm{e}}^{-\frac{1}{2}{\left(\mathrm{x}\right)}^{2}}\int_{\frac{{\upmu }_{\mathrm{M}}+{\upsigma }_{\mathrm{M}}\mathrm{x}-{\upmu }_{\mathrm{T}}}{{\upsigma }_{\mathrm{T}}}}^{\infty }\frac{1}{\sqrt{2\uppi }}{\mathrm{e}}^{-\frac{1}{2}{\mathrm{y}}^{2}}\mathrm{dydx}\end{aligned}$$
(3)

\({\mathrm{R}}_{1\mathrm{t}}^{1+}\) indicates that the traditional test method is used to test the DUT but is only tested once.

In the measurement of semiconductor product quality, DL can be used to represent the quality of semiconductor products. DL units are usually defined in PPM, DL = P[Bad | Pass] = P[(X > DS) ∩ (X < ST)] / P[X < ST].

$$\begin{aligned}\mathrm{DL }\left(\mathrm{Defect\ Level}\right)&=\frac{\mathrm{P}\left[\mathrm{Bad}|\mathrm{Pass}\right]}{{\mathrm{Y}}_{\mathrm{t}}}\\& =\frac{\mathrm{Missing\ Errors}}{{\mathrm{Y}}_{\mathrm{t}}}\\& =\frac{\int_{\mathrm{DS}}^{\infty }\mathrm{Chip}\left(\mathrm{x}\right)\int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{y}\right)\mathrm{dy\ dx}}{\int_{-\infty }^{\infty }\mathrm{Chip}\left(\mathrm{x}\right)\int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{y}\right)\mathrm{dydx}}\\& =\frac{\int_{\mathrm{DS}}^{\infty }\frac{1}{{\upsigma }_{\mathrm{M}}\sqrt{2\uppi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{x}-{\upmu }_{\mathrm{M}}\right)}^{2}}{2{{\upsigma }_{\mathrm{M}}}^{2}}}\int_{\mathrm{x}}^{\infty }\frac{1}{{\upsigma }_{\mathrm{T}}\sqrt{2\uppi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{y}-{\upmu }_{\mathrm{T}}\right)}^{2}}{2{{\upsigma }_{\mathrm{T}}}^{2}}}\mathrm{dydx}}{=\int_{-\infty }^{\infty }\frac{1}{\sqrt{2\uppi }}{\mathrm{e}}^{-\frac{1}{2}{\left(\mathrm{x}\right)}^{2}}\int_{\frac{{\upmu }_{\mathrm{M}}+{\upsigma }_{\mathrm{M}}\mathrm{x}-{\upmu }_{\mathrm{T}}}{{\upsigma }_{\mathrm{T}}}}^{\infty }\frac{1}{\sqrt{2\uppi }}{\mathrm{e}}^{-\frac{1}{2}{\mathrm{y}}^{2}}\mathrm{dydx}}\end{aligned}$$
(4)

3 Test Guardband (TGB) Decisions Affect Test Results

The trigger signal ST sent by the IC tester has an edge placement error due to the inaccuracy of the IC tester. In the testing process, the trigger signal sent by the IC tester is faster than the predetermined time of the IC tester, which will increase the probability of test errors in which the good product is judged as the failed product. Conversely, if the trigger signal sent by the ATE tester is slower than the time scheduled by the IC tester, then the probability of test errors for the bad product to be judged as a pass will increase. Therefore, the tester accuracy [24, 25] of the ATE tester must also be considered when using the IC tester to measure the DUT to be tested. The TGB must be emphasized considering the inaccuracy of the tester. Figure 5 shows the TGB, which is defined as the distance between the TS and the DS: TGB = DS − TS [26, 27]. Expanding the TGB (TGB ↑ = DS − TS) indicates changing the TS, which will increase killing errors and decrease missing errors. If the TGB is expanded in this manner, then the test quality (DL) will be improved and the test yield (Yt) will be decreased. On the contrary, we lowered the TGB (TGB ↓ = DS − TS). Such a small TGB will result in an increase in missing error and a decrease in killing error. Therefore, the test quality (DL) will become increasingly worse, resulting in a large number of customer returns. Thus, the choice of the TGB can be used as a reference for measuring the test yield (Yt) and test quality (DL).

Fig. 5
figure 5

Setting of the test guardband (TGB) affects the test yield (Yt) and test quality

For example, the circuit characteristic parameters of the chip are X ~ N (x; μM = 1000 ps and σM = 100 ps) to design a circuit whose design DS = 1165 ps. Following the estimated formula above, the manufacturing yield Ym = 95% can be obtained. If all are sold at will, then the defect rate DL will reach 50,000 ppm (100,000,000 × 5% = 50,000). Using the ATE tester characteristic parameter OTA = 120 ps, the TS is set to TS = μT = 1082 ps (TGB = 1165 − 1082 = 83 ps) through the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\) and the test yield Yt = P[Pass] = P[X < ST] = 77.76% and DL = 300 ppm test quality (DL), which is consistent with general central processing unit (CPU) quality.

Conversely, the test yield Yt = 63.42% and the test quality DL = 10 ppm can be obtained by setting the TS as 1037 ps (TGB = 1165 − 1037 = 128 ps) (Fig. 6 and Table 1). A large TGB guarantees the improved quality of the shipment. Although the number of products that passed the tester test decreased (due to the high rate of killing error), 14.34% (14.34 = 77.76 − 63.42%) loss of test yield (Yt) was exchanged for high-quality products. Using the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\) to move the TGB, the test yield (Yt) and test quality (DL) of the product are interchangeable but not both. Uncertain factors in the semiconductor process, product defects, and inaccuracy and operational problems in the testing process are also observed. Engineers can effectively reduce the defective products to a minimum only when they choose to test the guardband properly.

Fig. 6
figure 6

Test guardband (TGB) affects test results

Table 1 ATE tester to improve the test yield (Yt)

3.1 Ate Accuracy Affects IC Test Yield and Quality

Next, the chips are sent to the test house for analysis. OTA refers to the accuracy parameter specification of the ATE tester. A small OTA value [24, 25] leads to improved accuracy of the ATE tester. This condition indicates that the testing capability of the tester is superior to the semiconductor manufacturing capability. Similarly, a large OTA value leads to poor accuracy of the ATE tester, that is, the testing capability is lower than the manufacturing capability. We use different ATE testers below to examine the DUT. Figure 7 and Table 1 show the selected ATE tester characteristic parameter σT = 60 ps (a large σT leads to low accuracy) and OTA = 3 × σT = 180 ps. The product quality is set to DL = 300 ppm and the TS = 1028 ps is used. Through the above estimation formula, the test yield Yt = 59.52% can be obtained by the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\). A high-precision ATE tester whose characteristic parameters σT = 30 ps (a small σT indicates high accuracy) is then selected and the OTA = 3 × σT = 90 ps. The product quality was maintained at DL = 300 ppm and the DUT was tested using the test parameter TS = 1107 ps. The test yield Yt = 84.72% can be obtained through the above estimation formula. The high-precision ATE tester improves the test yield (Yt) by approximately 25.2% (84.72% − 59.52% = 25.2%).

Fig. 7
figure 7

Test specifications (TS) affect test results under general quality conditions (300 ppm)

Taking CPU desktop computer as an example, the quality requirement of DL = 300 − 200 ppm should be acceptable to manufacturers and consumers. However, some products, such as biomedical or automotive electronics, require high-standard quality requirements close to zero defects (10 ppm). Two ways are used to obtain high-quality chip products. Under the OTA = 30 ps test conditions, the first method uses the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\) and moves the TGB to test the DUT. For example, defect levels are limited to 10 ppm after the foundry fabrication and the TGB is moved and tested using traditional test methods \({\mathrm{R}}_{1\mathrm{t}}^{1+}\). According to the previously estimated formula for the test yield (Yt) estimation of the product, the test yield (Yt) drops to 75.83% (Fig. 8) when the TS μT = 1073 ps is used. A total of 8.9% (84.72% − 75.83% = 8.89%) of the test yield (Yt) is lost and a stable and high-quality chip is obtained. High-quality semiconductor chip products can be exchanged for superior and high sales prices, which introduce improved visibility and market reputation to manufacturers. Under the condition of the same product quality DL = 10 ppm, the second method is the ATE tester with high accuracy (a small σT leads to high accuracy) σT = 20 ps (the accuracy of the ATE tester OTA = 3 × σT = 60 ps) and the TS parameters are TS = 1106 ps are set. The test yield Yt = 85.14% can be obtained through the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\), which was approximately 9.31% (OTA20 − OTA30 = 85.14 − 75.83%) higher than that of the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\).

Fig. 8
figure 8

Influence of test specifications (TS) on test results under conditions of high-quality products (10 ppm)

The above results reveal that as the accuracy of the characteristic parameter (OTA) of the tester decreases, the test yield (Yt) will become increasingly worse and the problems of killing and missing errors will become highly serious. Conversely, the test yield (Yt) can be improved by approximately 25% when using a high-precision (OTA) tester. However, the price of the ATE tester is high and that of high accuracy (OTA) ATE tester can be as high as several million dollars. The tester adopts an hourly rental system, but an expensive tester raises the rental price. Based on market demand and response, in addition to considering test cost and test yield (Yt), selecting an appropriate and cost-effective ATE tester according to the circuit characteristics of the DUT to be tested is necessary for test decision-makers.

4 New Scheme of MRS

Critical electronic products require strict quality control to improve product reliability by eliminating all defects in the product population. However, according to the report introduced by the ITRS roadmap, the progress of the IC tester is still slower than that of the manufacturing process. Using existing instruments and tools to select electronic products with high reliability will be a considerable challenge for suppliers due to the slow development of test technology. At present, retesting has been widely used in test production lines to improve the shipment and test yield (Yt) chips. For example, Horng et al. [12] proposed a two-stage approach to ordinal optimization theory, in which sufficient values are obtained in a reasonable computation time, reducing overkill, and retesting problems. Cheng et al. [11] utilized machine learning algorithms to detect defect-inducing features automatically, thus utilizing re-testing of chips to improve yield. In addition, Selg et al. [13] proposed a method for applying machine learning to predict test–retest effectively. This method is utilized in the manufacture of real products, thus optimizing the manufacturing test time.

Therefore, under the premise of acceptable test costs, to improve product quality and test yield (Yt), we extended the test time and changed the test conditions and methods to enhance the test yield (Yt) by re-testing the chip. The decision-making process is shown in Fig. 9. First, starting the first test, all tested chips are divided into Pass DUT (P) part and Fail (F) DUT part. We conditionally retest the parts that pass the test (P) several times. Figure 9 shows the corresponding decision diagram, where the first passing chips were tested N times (i.e., different TS parameters). We call this method the “repeat test method.” The test result formula of retest \({(\mathrm{M}}_{\mathrm{nt}}^{\mathrm{np}})\) is defined as the following:

Fig. 9
figure 9

Decision diagram for the repeat test method

$$\begin{aligned}\mathrm{Retest\ Test\ Yield}\left(\mathrm{\%}\right){\mathrm{Y}}_{\mathrm{t}}&={(\mathrm{M}}_{\mathrm{nt}}^{\mathrm{np}})\\& =\int_{-\infty }^{\infty }\mathrm{Chip}\left(\mathrm{x}\right)\int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{y}, {\mu }_{\mathrm{T}1}\right)\mathrm{dy}\int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{z}, {\mu }_{\mathrm{T}2}\right)\mathrm{dz} \dots \dots \int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{w}, {\mu }_{\mathrm{Tn}}\right)\mathrm{dw\ dx}\\& =\int_{-\infty }^{\infty }\frac{1}{{\sigma }_{\mathrm{M}}\sqrt{2\pi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{x}-{\mu }_{\mathrm{M}}\right)}^{2}}{2{{\sigma }_{\mathrm{M}}}^{2}}}\int_{\mathrm{x}}^{\infty }\frac{1}{{\sigma }_{\mathrm{T}}\sqrt{2\pi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{y}-{\mu }_{\mathrm{T}1}\right)}^{2}}{2{{\sigma }_{\mathrm{T}}}^{2}}}\mathrm{dy}\int_{\mathrm{x}}^{\infty }\frac{1}{{\sigma }_{\mathrm{T}}\sqrt{2\pi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{z}-{\mu }_{\mathrm{T}2}\right)}^{2}}{2{{\sigma }_{\mathrm{T}}}^{2}}}\mathrm{dz}\dots \dots \\& \cdots \cdots \cdots \cdots \int_{\mathrm{x}}^{\infty }\frac{1}{{\sigma }_{\mathrm{T}}\sqrt{2\pi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{w}-{\mu }_{\mathrm{Tn}}\right)}^{2}}{2{{\sigma }_{\mathrm{T}}}^{2}}}\mathrm{dwdx}\end{aligned}$$
(5)
$$\begin{aligned}\mathrm{Retest\ DL}\ \left(\mathrm{Defect\ Level}\right)&={(\mathrm{M}}_{\mathrm{nt}}^{\mathrm{np}}) \\& =\frac{\mathrm{Missing\ Errors}}{{\mathrm{Y}}_{\mathrm{t}}}\\& =\frac{\int_{\mathrm{DS}}^{\infty }\mathrm{Chip}\left(\mathrm{x}\right)\int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{y},\ {\upmu }_{\mathrm{T}1}\right)\mathrm{dy}\int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{z},\ {\upmu }_{\mathrm{T}2}\right)\mathrm{dz}\dots \int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{w},\ {\upmu }_{\mathrm{Tn}}\right)\mathrm{dw\ dx}}{\int_{-\infty }^{\infty }\mathrm{Chip}\left(\mathrm{x}\right)\int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{y},\ {\upmu }_{\mathrm{T}1}\right)\mathrm{dy}\int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{z},\ {\upmu }_{\mathrm{T}2}\right)\mathrm{dz}\dots \int_{\mathrm{x}}^{\infty }\mathrm{Tester}\left(\mathrm{w},\ {\upmu }_{\mathrm{Tn}}\right)\mathrm{dw\ dx}}\\& =\frac{\int_{\mathrm{DS}}^{\infty }\frac{1}{{\upsigma }_{\mathrm{M}}\sqrt{2\uppi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{x}-{\upmu }_{\mathrm{M}}\right)}^{2}}{2{{\upsigma }_{\mathrm{M}}}^{2}}}\int_{\mathrm{x}}^{\infty }\frac{1}{{\upsigma }_{\mathrm{T}}\sqrt{2\uppi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{y}-{\upmu }_{\mathrm{T}1}\right)}^{2}}{2{{\upsigma }_{\mathrm{T}}}^{2}}}\mathrm{dy}\int_{\mathrm{x}}^{\infty }\frac{1}{{\upsigma }_{\mathrm{T}}\sqrt{2\uppi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{z}-{\upmu }_{\mathrm{T}2}\right)}^{2}}{2{{\upsigma }_{\mathrm{T}}}^{2}}}\mathrm{dz}\ \dots\ \dots\ \dots\ \dots\ .}{\int_{-\infty }^{\infty }\frac{1}{\sqrt{2\uppi }}{\mathrm{e}}^{-\frac{1}{2}{\left(\mathrm{x}\right)}^{2}}\int_{\frac{{\upmu }_{\mathrm{M}}+{\upsigma }_{\mathrm{M}}\mathrm{x}-{\upmu }_{\mathrm{T}1}}{{\upsigma }_{\mathrm{T}}}}^{\infty }\frac{1}{\sqrt{2\uppi }}{\mathrm{e}}^{-\frac{1}{2}{\mathrm{y}}^{2}}\mathrm{dy}\int_{\frac{{\upmu }_{\mathrm{M}}+{\upsigma }_{\mathrm{M}}\mathrm{x}-{\upmu }_{\mathrm{T}2}}{{\upsigma }_{\mathrm{T}}}}^{\infty }\frac{1}{\sqrt{2\uppi }}{\mathrm{e}}^{-\frac{1}{2}{\mathrm{z}}^{2}}\mathrm{dz}\dots\ \dots\ \dots\ \dots\ .}\\& \frac{\dots\ \dots\ \dots\ \dots\ \int_{\mathrm{x}}^{\infty }\frac{1}{{\upsigma }_{\mathrm{T}}\sqrt{2\uppi }}{\mathrm{e}}^{\frac{-{\left(\mathrm{w}-{\upmu }_{\mathrm{Tn}}\right)}^{2}}{2{{\upsigma }_{\mathrm{T}}}^{2}}}\mathrm{dwdx}}{\dots\ \dots\ \dots\ \int_{\frac{{\upmu }_{\mathrm{M}}+{\upsigma }_{\mathrm{M}}\mathrm{x}-{\upmu }_{\mathrm{Tn}}}{{\upsigma }_{\mathrm{T}}}}^{\infty }\frac{1}{\sqrt{2\uppi }}{\mathrm{e}}^{-\frac{1}{2}{\mathrm{w}}^{2}}\mathrm{dwdx}}\end{aligned}$$
(6)

4.1 Flowchart for MRS Decision Making

The application of repeated testing through the actual production line [10] can improve the test yield (Yt) and quality. However, the test costs will increase with the number of tests. Furthermore, the repeated testing method is unnecessary when the cost of testing outweighs the added profit. Unlimited retesting is also called blind testing, which not only wastes manpower but also increases testing costs. Therefore, the test yield (Yt) and the test cost must be considered when implementing the retest method. Furthermore, choosing an effective number of retests and avoiding blind retests is necessary to obtain the highest cost-effectiveness. Therefore, under the premise of an acceptable test cost, we have changed the test conditions and methods, extended the test time, and proposed an MRS to retest the chip to improve the test yield (Yt) of the chip. This test system is based on the test method for retesting (Fig. 9) and adds a mechanism for calculating the profit cost. The optimal number of retests is determined through sequential analysis of the flowchart according to the obtained test cost and test yield (Yt). The execution steps of the MRS are presented as follows (Figs. 10 and 11).

Fig. 10
figure 10

Flowchart of multiple retest system (MRS) decision making

Fig. 11
figure 11

Execution flowchart of multiple repetition system

Step 1

First, we perform the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\) on the DUT and then estimate the test yield (Yt) and test quality (DL) of the traditional test method. We take the obtained results using the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\) as a reference value and compare them with the test results of the next stage retest.

Step 2

Next, we test the DUT using the test method for retesting and moving the guardband (i.e., different TS parameters). This step utilizes the moving TGB to reduce killing and missing errors and improve test quality (DL) and test yield (Yt).

Step 3

We then calculate the profit cost according to the obtained test cost and test yield (Yt). We will determine the optimal number of retests through sequential analysis of the flowchart. Such a step can help avoid blind retests, save labor, time, and testing costs, and assist in finding the optimal number of retests.

Step 4

The DITM model contains many complex parameters and the calculations of manufacturing yield (Ym) and test yield (Yt) are cumbersome. Small changes in electrical parameter values can lead to large changes in yield estimates. Therefore, we use the approximate search method to adjust the TS value of the test and obtain the highest test yield (Yt) and the best profit by adjusting the best test protection.

Step 5

The proposed MRS is established considering that the improved profit is larger than the testing cost. Therefore, through repeated test methods and cost calculations, we can determine that the (MRS) test system can maximize test yields (Yt) and maximize company profits.

4.2 Selection and Setting Mechanism of Test Specifications (Approximate Search Method)

The ST sent by the tester during the test process would have edge placement due to the problem of tester inaccuracy. When the ST tester is faster than the time set by the tester, the testing error probability of determining “good” as “fail” would increase; on the contrary, when the ST sent by the tester is slower than the time set by the tester, then the testing error probability of determining “bad” as “pass” would increase. Thus, the accuracy of the tester should also be considered when using testers to measure the DUT. The inaccuracy of the tester leads to killing and missing errors. Therefore, the test engineer must weigh the movement of the test guard to reduce the probability of errors. Moreover, the expansion of TGB will improve the test quality and reduce the test yield, TGB can be used as a tradeoff factor between test quality and yield.

Selecting a test point is important to satisfy the custom’s requirement. First, the scope of the test quality is set, and then the movement of the TGB is used to find the appropriate TSs. When using traditional testing method, TGB could be changed and moved while product test yield and quality could be exchanged but could not be obtained concurrently. Defective manufacturing would lead to product defects; therefore, adjusting the TGB appropriately during the test process is necessary to eliminate most of the defective products. When the MRS method is used to test the DUT, the most important issue is to choose the appropriate TS because the TS will affect the test yield and quality. The digital integrated circuit testing model (DITM) contains many complicated parameters; thus, the calculations of manufacturing and test yields are complicated. A slight change in the value of a parameter will lead to a substantial change in the calculation result. Therefore, an approximate search method was used to determine the TS value for the traditional test method (Figs. 12 and 13).

Fig. 12
figure 12

Flow chart for determining test specifications (TS)

Fig. 13
figure 13

Optimal test specification (approximate search method) selection and setup mechanisms

An example is a chip with a DS of (0.86 GHz) 1165 ps and circuit property parameter of X ~ N(x; μM = 1000 ps, σM = 100 ps), as well as the above-mentioned estimated formula was used. The manufacturing yield was 95% (Fig. 12 and Table 2). Before selecting the test specifications (TS), the product quality must be considered, and the quality value must be set (DL = 300 ppm). Subsequently, numerical approximation was employed to find the TSs (Fig. 12). The DUT was also tested using ATE (overall timing accuracy (OTA) = 3 × σT = 120 ps, then σT = 40 ps). The average of ST is equal to TS, μT = TS. As a result, the decision of TSs was related to testing yield and quality. In this evaluation, TSs only played the role of mediator. However, corresponding information for the DS parameter could be provided and the information could be expressed clearly and conveniently by using the specification parameter. The standard deviation of ST was obtained from tester accuracy, and overall timing accuracy (OTA) (overall timing accuracy) was the specification parameter of the tester accuracy in this study (assuming OTA = 3 × σT = 120 ps and so σT = 40 ps). TGB is defined as the distance between the test and DSs if ti is tested (TGB = DS – TS). This distance is three times larger than the tester ST standard deviation (σT), namely TGB = 3 × σT = 40 ps = OTA. Thus, the test specifications are as follows: TS = 1165 − 40 = 1125 ps, namely ST ~ N(μT, σT) = N(1125 ps, 40 ps). Next, four test points were selected (DS – 3 × σT; TS = DS – 2 × σT; TS = DS – 1 × σT; TS = DS), the DUTs were tested separately (Table 2), and the individual test findings of the four test points were estimated (DS – 3 × σT = 1045 ps, DL = 20 ppm; TS = DS – 2 × σT = 1085 ps, DL = 356 ppm; TS = DS – 1 × σT = 1125 ps, DL = 2918 ppm; TS = DS = 1165 ps, DL = 11,756 ppm). Between TS = DS – 2 × σT (DL = 356 ppm) and TS = DS – 3 × σT (DL = 20 ppm) test specifications, the required test quality could be obtained (DL = 300 ppm). Therefore, the product conformed to the quality conditions, and the best TSs were discovered (μT1 = 1083 ps), the obtained test yield (Yt) was 77.8%. Next, the TGB was moved, and the test range was narrowed based on the above DL and TSs. Finally, the product conformed to the quality conditions, and the \({\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}\) best TSs were found (μT1 = 1083 ps, μT2 = 1100 ps, and μT3 = 1101 ps), the obtained test yield (Yt) was 83.24% while the desired DL (300 ppm) was maintained, and the yield improved by 17.2% (83.24% − 77.8% = 5.44%). When strict TSs are used, the test pass rate is reduced while the test quality is relatively improved. Assuming that the TGB is lowered, that is, a loose TS is applied, the test pass rate will increase and the test quality will be relatively reduced. The above analysis shows that the TSs directly affect the final test yield. Hence, test engineers must be careful in choosing TSs (test guardband).

Table 2 Test specifications and methods affect test results

4.3 Most Cost-effective Retest System (MRS)

The purpose of the test is to identify the chip's characteristics and value, such as its highest frequency, power consumption, and processor level. However, with the continuous advancement of the semiconductor manufacturing process and packaging technology, not only are the functions of the chip increasing, but the chip's speed is also increasing. Therefore, effectively testing the yield, and quality of the wafer becomes extremely complicated. Furthermore, the design, and function of ultra-large-scale integrated circuit chips are increasingly complicated. The greater the number of test items covered, the higher the proportion of test cost to wafer manufacturing cost. However, how to reduce testing costs through effective testing strategies has become a very important issue. As a result, chip suppliers must strive to strike a balance between quality and profit, improve chip yield, and pursue high quality with a high profit as the end goal.

However, the progress of IC tester is slow to almost stagnant in the rapidly advancing semiconductor industry. How to reduce product defect rates and distinguish high-quality chips has also become a critical issue. Therefore, the testing industry invests more funds and manpower, especially in IC tester updates and breakthroughs in test methods. Although, retesting has been widely used in wafer testing, and obtained quite good yield improvement results. However, the more times retested, the higher the cost of labor and IC tester rental. If the total cost of testing exceeds the profit from wafer sales, the retest method has no meaning. Although the speed of testing wafers of the IC tester is very fast, wafer production is in millions. However, the retesting time and the tester rental cost will increase multiple times, causing the company's profits to be compressed. Therefore, before the test, cost control, and profit estimation must be considered. Following that, we seek the best profit and loss balance point for the cost problem and the increased profit of retesting. We use the cost calculation and take to find the optimal number of tests. It does not only consider the cost of testing and the best benefit of retesting, but it also improves the test yield.

The calculation method of 8:20 [28] is used considering the chip pricing in the international market. For example, an IC that is sold for $20 costs $8 to manufacture. In the manufacturing process of semiconductor chips, the cost of chip testing accounts for approximately 5% of the total manufacturing cost [20]. Assuming Company “C” produces 100 million chips per year, if each chip costs $8 to manufacture, then the total cost of testing required by company “C” is approximately $40 million (100,000,000 × 8 × 5% = $40,000,000).

For example, the design house created a chip with DS = 1165 ps (0.858 GHz) with electrical parameters X ~ N (x; μM = 1000 ps and σM = 100 ps). Using the estimated Eqs. (1)–(2) above, we obtained a manufacturing yield of Ym = 95% (Fig. 14 and Table 3). The test quality DL was set to 300 ppm and an IC tester with OTA = 120 ps was chosen to test the DUT. We adopt the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\) and set the TS to 1082 ps, which yields Yt = 77.76%.

Fig. 14
figure 14

Number of retests determines the test yield

Table 3 Estimation of test costs for multiple repetition systems

As shown in Fig. 14, under the same test conditions (DL = 300 ppm and OTA = 120 ps), we set the TS value (μT1 = 1124 ps, and μT2 = 1126 ps) and used the repeated test \({(\mathrm{M}}_{2\mathrm{t}}^{2\mathrm{p}})\) to test the DUT, based on the above estimates. The test yield is improved from Yt = 77.76% (\({\mathrm{R}}_{1\mathrm{t}}^{1+}\)) to Yt = 83.47% \({(\mathrm{M}}_{2\mathrm{t}}^{2\mathrm{p}}\)) after estimation. The company can increase its sales by 5,710,000 chips (100,000,000 × 5.71% = 5.71 million) per year after our iterative estimation. Therefore, the company generates an additional annual revenue of $114.2 million per year (100,000,000 × 20 × 5.71% = 114.2 million). The company could earn an additional $34.2 million (114.2 − 40 − 40 = $34.2 million) after deducting the testing cost of the two retests. Next, we test the DUT using the retest \({(\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}})\) method. Setting the TS value (μT1 = 1142 ps, μT2 = 1146 ps, and μT3 = 1148 ps) to test the DUT, the retest method can improve the test yield from Yt = 77.76% (\({\mathrm{R}}_{1\mathrm{t}}^{1+}\)) to Yt = 85.6% (\({\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}\)). The test yield (Yt) increased by 7.84% (85.6% − 77.76% = 7.84%), resulting in an additional $36.8 million in revenue after deducting the cost of three repeat tests (156.8 − 40 − 40 − 40 = $36.8 million). Next, we test the DUT with repeated test \({(\mathrm{M}}_{4\mathrm{t}}^{4\mathrm{p}})\) (TS μT1 = 1156 ps, μT2 = 1155 ps, μT3 = 1158 ps, and μT4 = 1159 ps), and the test yield (Yt) can be improved from 77.76% (\({\mathrm{R}}_{1\mathrm{t}}^{1+}\)) to 86.76%(\({(\mathrm{M}}_{4\mathrm{t}}^{4\mathrm{p}}\)). The total profit is lower than that of the retest \({\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}\) test method ($36.8 million > $20 million) after deducting the cost of testing (180 − 40 − 40 − 40 − 40 = $20 million). We also compared the test results of different test–retest methods \({({\mathrm{R}}_{1\mathrm{t}}^{1+},\mathrm{M}}_{2\mathrm{t}}^{2\mathrm{p}}, {\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}{,\ \mathrm{and\ M}}_{4\mathrm{t}}^{4\mathrm{p}})\) under the same quality DL = 300 ppm. The retest plan \({(\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}\)) can improve the best test results and obtain the best company profit under the condition of 300 ppm quality.

Due to the stagnation of testing capabilities, how the IC tester can distinguish between good and bad objects under test (IC) will become an important issue. An effective Multiple Retest Systems test method is proposed to enhance the test yield, which can effectively improve the test results by utilizing the mobile test guardband (Fig. 5) and prolonging the test time. First, narrow down the test specification (TGB↓, α↓, Yt↑) and perform the first test of the DUT. The occurrence of killing errors can be reduced by moving the test guardband, thereby improving the test yield. On the other hand, the movement of the test guardband directly affects the test results. Therefore, the number of chips in the pass part increases, while the number of chips in the missing error part also increases (β↑). Therefore, removing the bad chips (missing errors) in the past part becomes the main purpose of the second and third retests. Next, the second, and third tests are carried out on the object to be tested. Similarly, we improve the test yield and test quality (reduce missing errors) by fine-tuning the test guard (test specification). By reducing killing errors (α↓) and missing errors (β↓), the problem of test yield can be solved, and the ability of the IC tester can be improved. However, when entering the fourth retest phase. Although the test yield has increased slightly, the growth rate is too small. The profit generated by a slight increase in yield rate is less than the cost of testing, so overall profit will naturally decline. Therefore, three retests are not only cost effective but also increase the maximum commercial profit. We can conclude from the above inferences that using the Multiple Retest test method and an appropriate test protection area (approximate search method) can solve the problems of missing errors and killing errors, thereby improving the test yield and test quality. The Multiple Retest test method removes abnormal parts from the total parts under the requirement of equal quality DL by moving the test guardband (changing the test specifications). The increase in the number of retests and the appropriate movement of the test guardband improve not only the test capability of the IC tester but also the test yield. In other words, increasing the test time (Test Time) and increasing the number of tests can reduce the probability of killing and missing errors, and improve the test results. From the simulation outcome, the appropriate number of retests is interchangeable with accurate test guard band movement, test yield quality, and test time.

Next, the above simulation test is repeated on the same test equipment with the quality set at DL = 10 ppm for high-quality products. As shown in Fig. 15, under high-quality test conditions (DL = 10 ppm and OTA = 120 ps), we set the TS value (μT1 = 1112 ps, μT2 = 1115 ps, and μT3 = 1119 ps) and used the repeated test \({(\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}})\) to test the DUT based on the above estimates. The test yield (Yt) is improved from Yt = 63.4% (\({\mathrm{R}}_{1\mathrm{t}}^{1+}\)) to Yt = 78.22% \({(\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}\)) after estimation. The company could earn an additional $247.4 million (296.4 − 40 − 40 − 40 = $176.4 million) after the cost of testing for two retests is deducted. We also compared the test results of different test–retest methods \({({\mathrm{R}}_{1\mathrm{t}}^{1+},\mathrm{M}}_{2\mathrm{t}}^{2\mathrm{p}}, {\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}{\mathrm{ and M}}_{4\mathrm{t}}^{4\mathrm{p}})\) at the same quality DL = 10 ppm. The retest plan \({(\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}\)) can improve the best test results and obtain the best company profits under the condition of 10 ppm high quality. In addition, at high quality (10 ppm), the improved yield and company profits achieved using the retest method are far larger than those achieved by general test quality (300 ppm). Therefore, we confirm that the retest plan (\({\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}\)) is the best test plan after the above simulation and test results.

Fig. 15
figure 15

Calculation of the best cost-effectiveness of the multiple repetition system

Undoubtedly, as shown in Fig. 16 clearly shows where the break-even point occurs and how the optimal number of tests varies with testing cost. The graph drawn by the above estimates illustrates the optimal number of retests taking both profit and cost into account. Whether it is general test quality (300 ppm) or high-quality product testing (10 ppm), retesting the plan three times can achieve not only the best profit and loss balance but also the best profit. That is to say, the occurrence of killing errors and missing errors is reduced by moving the test guard band and changing the test method. Not only has the test yield rate been improved, but a profit greater than the retest cost will open up business opportunities for the company.

Fig. 16
figure 16

How the optimal number of test passes would change as a function of test cost

The above results reveal that the repeated test method can improve the test yield (Yt). However, the test cost increases with the repetition of test times. When the cost of testing is larger than the profit added by testing, the testing method will not help the company’s contribution and profit despite its effectiveness. Therefore, we must choose an appropriate number of tests while avoiding blind retesting. On the basis of cost estimation and judgment, the MRS test strategy can reduce the test cost, save workforce and time, and improve the profit of the best company.

5 Multiplex Test Method (MRS) Applied to the IRDS 2021 Data

The development of IC products is rapidly accelerating, and the semiconductor process has been developed from 90 to 7 nm. Test verification of chips has become an important issue due to the increasing complexity of chip functions. However, using slow-moving testers to distinguish between good and bad chips has become increasingly inaccurate due to the differences in the development of test and manufacturing technologies. Furthermore, the inaccuracy of the ATE tester (IC tester) will lead to additional yield losses. Therefore, utilizing existing semiconductor test equipment (IC tester) (with insufficient test capabilities) to achieve zero-defect products is a growing challenge for suppliers. Therefore, seeking an effective solution and improving the performance of the VLSI tester is currently a crucial topic. We propose an MRS solution to maximize test yield (Yt) and test quality (DL) to address the product quality requirements of consumers. Furthermore, we can accurately predict the future test yield (Yt) of the chip through reliable data and estimation methods (DITM). We can propose additional effective testing methods and develop remarkably advanced testing equipment by estimating the trend curve of future yield rates. The test results and company profits can also be aligned with the future goals of the company by proposing additional effective test methods in advance.

Table 4 shows the data of the estimated electrical parameters of IRDS 2021 chips [23]; thus, DITM is utilized to estimate the test yield (Yt) of future chips. The product DUT electrical characteristic parameters in 2022, wherein the DS is 3.3 GHz (303 ps), the average μM = 195 ps, and the standard deviation σM = 65 ps, are also used. We can obtain the production yield of 95% (Ym) according to the estimated formula above. Next, we use a tester with OTA = 100 ps to test the DUT under the condition that the quality is set by the manufacturer as 300 ppm (Fig. 17 and Table 4). The TS is set to 230 ps, and the test yield (Yt) of 68.4% can be obtained through the iterative estimation of formula (3).

Table 4 Comparison of traditional testing methods and multiple testing \({(\mathrm{M}}_{3\mathrm{t}}^{3\mathrm{p}}\)) under the 300 and 10 ppm test quality (DL) conditions
Fig. 17
figure 17

MRS applied to the IRDS table [23] for guardbanding (300 and 10 ppm)

Using DITM to estimate the future product test yield (IRDS 2021), the slow progress of the tester is found to be relative to the rapid progress of the process and the test yield (Yt) will become increasingly worse. The testing technology is also far behind the semiconductor process technology. Thus, using an ATE tester whose performance lags behind the process capability for selecting high-reliability electronic products will be a big challenge. IC test manufacturers must perform strict quality control to ensure the reliability of key automotive or biomedical electronic products. Therefore, we change the test method and introduce the MRS. The test yield (Yt) can be effectively improved without sacrificing the test quality (DL) by relaxing the TS. Referring to the IRDS 2022 product DUT electrical characteristic parameters, we estimated the test yield (Yt) of chips produced in 2022 using the MRS after changing the test method under the same ATE equipment (OTA = 100 ps). The MRS achieved a test yield (Yt) of 80.9%, which was approximately 12.5% higher than that of the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\) (68.4%).

We will use the MRS as shown below to estimate the additional profit provided by the semiconductor company on a cost basis. For example, suppose “C” Semiconductor Company produces 100 million chips per year and uses an 8:20 international chip pricing strategy. In this case, if the manufacturing cost per chip is $8, then the selling price per chip is $20. Referring to IRDS estimates, the test cost per chip is 5% of the manufacturing cost; therefore, the total cost of testing for 100 million chips is approximately $40 million (100,000,000 × 8 × 5% = $40,000,000). Referring to the above example (Estimate the chip production in 2022 (IRDS in 2021)), we will then estimate the additional profit provided by semiconductor companies after deducting test costs. Next, after deducting the cost of retesting three tests, repeating the test can increase the profit by $130 million (100 million × 20 × 12.5% = $250 million, 250 − 40 − 40 − 40 = $130 million). We then estimate the chip production in 2025 (IRDS in 2021). The test yield will increase to Yt = 78.3% by using the MRS method to test the DUT. The MRS improves the test yield (Yt) by approximately 14.7% (78.3% − 63.6% = 14.7%). Next, after deducting the cost of retesting three tests, repeating the test can increase the profit by $174 million (100 million × 20 × 14.7% = $294 million, 294 − 40 − 40 − 40 = $174 million). The estimated results reveal that an MRS can significantly improve the test yield (Yt). By contrast, the use of a TGB can reduce the incidence of detection and killing errors and achieve high-yield delivery and the overall revenue and profits of the company will be significantly improved.

5.1 Improved Yield and Increased Profits for High-quality Chips

Reducing the defect rate of chips can reduce the malfunction of electronic parts and improve driving safety. Cars require ultrahigh levels of reliability and safety [5,6,7,8,9], thus, the auto industry is setting tough goals for “zero defects” in chips. Defect-free chips not only provide stable and safe operation of automotive electronics but also help companies gain improved reputation and high profits. Therefore, we propose an MRS testing method, which utilizes a slightly backward ATE tester and a retesting mechanism to find truly zero-defect and reliable products, to pursue zero-defect high-quality chips. We then set product quality requirements at high specification DL = 10 ppm and use the same ATE test equipment to test the DUT (OTA = 100 ps). Referring to the product DUT electrical characteristics parameters in 2022, the TS is set to 193 ps and the test yield (Yt) of 48.9% can be obtained through the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\). Next, the test yield (Yt) for chips produced in 2022 was re-estimated using the MRS method. After estimation, the test yield (Yt) of the MRS reaches 70.2%, which is approximately 21.3% higher than that of the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\) (48.9%). After deducting the test cost of retesting three times, the retest method can add 306 million US dollars to the profit.

Referring to the DUT electrical characteristic parameters of the product in 2025, the TS is set to 166 ps through the traditional test method \({\mathrm{R}}_{1\mathrm{t}}^{1+}\) and a test yield (Yt) of 42.5% can be obtained (Fig. 17 and Table 4). Testing the DUT using the MRS increases the test yield to Yt = 66.1%. The MRS also improved test yield (Yt) by approximately 23.6% (66.1% − 42.5% = 23.6%). After deducting the test cost of retesting three times, the retest method can increase the profit by 352 million US dollars. After estimating and comparing different qualities (10 and 300 ppm), we found that the yield and improved profit obtained using the retest method are far larger than the results obtained from the general test quality (300 ppm) under the condition of 10 ppm high quality. That is to say, under the condition of 10 ppm high quality, the retest plan (MRS) can markedly improve the test results and obtain the best company profits.

The retest method has been widely used in the testing of semiconductor ICs and can effectively improve the test yield (Yt) and test quality (DL). However, endless blind retesting may reduce the profit of the company and even cause the testing cost to exceed the retesting profit. Therefore, we propose multiple test schemes to meet consumer demand for the expected product output (MRS). The above simulation results reveal that changing the test method changed and relaxing the TS can effectively improve the test yield (Yt) without sacrificing the test quality (DL). Owing to the repeated inspection of the chip, the number of chips with killing errors is reduced, which not only effectively improves the test yield (Yt) but also enhances the test quality (DL). In addition, the costing of the retest method verified that the multiple test system (MRS) solution can maximize the test yield (Yt) by improving the performance of the automated test equipment (ATE) and maximizing company profits. Considering improving the test yield (Yt), the best balance of increasing profit and reducing test costs is achieved through the MRS mechanism.

5.2 The Innovations and Advantages of Multiple Retest Systems

The development speed of automated test equipment (ATE) (OTA, overall timing accuracy), according to the ITRS report, lags behind the progress speed of semiconductor manufacturing. The testing ability of the automated test equipment (ATE) is backward and insufficient, just like using a ruler with an inaccurate scale to measure an item with a precision greater than it, this will reduce the accuracy of the measurement. Consequently, we propose multiple test system (MRS), which can not only improve test yield but also test machine capability. The MRS retesting schemes can not only reduce the test cost but also greatly increase the test yield. Because the number of high-quality products that can be sold increase, but also increase the company's profits. The innovations and advantages of Multiple Retest Systems include the following

  1. 1.

    According to the cost feedback calculation, the optimal retest times can be calculated to save manpower and cost.

  2. 2.

    Move the test guardband (TGB) using the approximate search method, which is easy to use and fast in operation.

  3. 3.

    Save more testing costs and increase profits.

  4. 4.

    The maximum benefit between the profit and the test cost can be obtained.

  5. 5.

    Enhance the testing capability of the IC tester.

  6. 6.

    When used in high-quality chip testing (as in automotive aviation and electronics), the yield rate can be increased even further.

  7. 7.

    More company profits can be increased through high-level and high-quality wafer testing.

6 Conclusion

We propose a test model for digital semiconductor chips, which can effectively analyze the impact of different test parameters on quality and yield. We also describe the impact of ATE tester accuracy and TGB on test yield (Yt) and quality. In addition, the DITM model and the data provided by IRDS 2021 are used to estimate the future test yield (Yt) trend of semiconductor chips. Therefore, test manufacturers can improve the performance of ATE testers in advance and propose superior test methods by effectively predicting the future Yt. According to ITRS roadmap estimates, the testing capability has failed to keep up with the capability of the semiconductor process. In the future, if no breakthrough development in the testing methods of chips emerges, then the test yield (Yt) will become increasingly worse due to the inaccuracy of the ATE tester. Therefore, major manufacturers are also actively seeking effective testing methods to address the problem of insufficient testing capabilities. However, the retest is not only widely used in the testing of actual semiconductor production lines but can also markedly improve the test yield (Yt) and test quality (DL) through its application to actual production lines [10]. The MRS is proposed considering high-yield product testing methods; this system overturns the traditional theoretical concepts of yield-for-quality and quality-for-yield. The ATE tester with ordinary performance is used to improve the yield after the test effectively, and the method for moving the TGB is repeated to find a truly zero-defect and reliable product, thus achieving high-quality, zero-defect goals for avionics and biomedical electronics with cost estimation and effective retesting. The MRS can reduce the occurrence of killing and missing errors and the cost of testing. By contrast, the improvement in test yield (Yt) increases the number of chips sold, which not only raises sales profits but also enables the selection of additional high-quality chips.