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Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation

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Abstract

As the ICs become more complex, the duration of high-cost specification tests is increasingly important, especially given the total IC expenditure. In our current work, we propose an adaptive test strategy for reducing the duration of delay testing. This method employs pattern permutation with an ML algorithm to improve the test efficiency, followed by an examination of the effect of test performance, temperature, and voltage on the recognition of path delay defects. SPICE simulations under different voltage and temperature conditions with 65-nm CMOS technology were used to validate it. According to the experimental outcomes, when compared to the random ordering method, the proposed method successfully achieves a nearly 7-fold improvement in test quality at identical testing duration or a 25% reduction in the duration at identical test quality. In addition, the method provides the tester with a thorough understanding of the test efficiency contributions.

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Data Availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

Abbreviations

AT:

Adaptive test

LR:

List Reward

TE:

Test escape

ICs:

Integrated circuits

DPPM:

Defect part per million

ATE:

Automatic Test Equipment

ATPG:

Automatic test pattern generation

VT:

Voltage and Temperature

ML:

Machine learning

CUT:

Circuit under test

FPSA:

Failure pattern selecting algorithm

PMatch:

Permutation-Matching

PRank:

Permutation-Ranking

CNF:

Conjunctive normal form

OTA:

Operational transconductance amplifier

DPWN:

Deep Permutation-Wise Network

\(V_{DD}\) :

Supply voltage

LNA:

Low noise amplifier

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Funding

This work was supported by China Scholarship Council under the CSC No. 202206505003 and in part by the Cooperative Education Project of the Ministry of Education No.220803303162437 and in part by the National Natural Science Foundation of China under the Granted No. 62274052.

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Correspondence to Tai Song.

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Song, T., Huang, Z., Guo, X. et al. Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation. J Electron Test 39, 189–205 (2023). https://doi.org/10.1007/s10836-023-06057-8

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