Skip to main content

Advertisement

Springer Nature Link
Log in

Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

As the ICs become more complex, the duration of high-cost specification tests is increasingly important, especially given the total IC expenditure. In our current work, we propose an adaptive test strategy for reducing the duration of delay testing. This method employs pattern permutation with an ML algorithm to improve the test efficiency, followed by an examination of the effect of test performance, temperature, and voltage on the recognition of path delay defects. SPICE simulations under different voltage and temperature conditions with 65-nm CMOS technology were used to validate it. According to the experimental outcomes, when compared to the random ordering method, the proposed method successfully achieves a nearly 7-fold improvement in test quality at identical testing duration or a 25% reduction in the duration at identical test quality. In addition, the method provides the tester with a thorough understanding of the test efficiency contributions.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

Data Availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

Abbreviations

AT:

Adaptive test

LR:

List Reward

TE:

Test escape

ICs:

Integrated circuits

DPPM:

Defect part per million

ATE:

Automatic Test Equipment

ATPG:

Automatic test pattern generation

VT:

Voltage and Temperature

ML:

Machine learning

CUT:

Circuit under test

FPSA:

Failure pattern selecting algorithm

PMatch:

Permutation-Matching

PRank:

Permutation-Ranking

CNF:

Conjunctive normal form

OTA:

Operational transconductance amplifier

DPWN:

Deep Permutation-Wise Network

\(V_{DD}\) :

Supply voltage

LNA:

Low noise amplifier

References

  1. Biswas S, Li P, Blanton R, Pileggi L (2005) Specification test compaction for analog circuits and mems [accelerometer and opamp examples]. In Proc Des Automat Test Eur 1:164–169

    Article  Google Scholar 

  2. Chen M, Orailoglu A (2008) Test cost minimization through adaptive test development. In Proc. IEEE Int Conf Circuit Des 234-239

  3. Cheng X, Song R, Xie G, Zhang Y, Zhang Z (2018) A new FPGA-based segmented delay-line DPWM with compensation for critical path delays. In IEEE Transactions on Power Electronics 33(12):10794–10802

    Article  Google Scholar 

  4. Heo J, Kim T (2021) Reusable delay path synthesis for lightening asynchronous pipeline controller. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 7, pp. 1437-1450

  5. Huang NC, Cheng CW, Wu KC (2022) Timing variability-aware analysis and optimization for variable-latency designs. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 1, pp. 81-94

  6. Huang L, Song T, Jiang T (2022) Linear regression combined KNN algorithm to identify latent defects for imbalance data of ICs. Microelectron J 105641, ISSN 0026-2692,.mejo.2022.105641

  7. Javvaji PK, Tragoudas S (2019) On the sensitization probability of a critical path considering process variations and path correlations. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 5, pp. 1196-1205

  8. Karel A, Comte M, Galliere JM, Azais F, Renovell M (2017) Influence of body-biasing, supply voltage, and temperature on the detection of resistive short defects in FDSOI Technology. In IEEE Transactions on Nanotechnology 16(3):417–430

    Article  Google Scholar 

  9. Larrabee T (1992) Test pattern generation using Boolean satisfiablity. IEEE Trans Comput-Aided Des Integr Circuits Syst 11(1):4-15

  10. Ma J, Tehranipoor M (2011) Layout-aware critical path delay test under maximum power supply noise Effects. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30(12):1923–1934. https://doi.org/10.1109/TCAD.2011.2163159

    Article  Google Scholar 

  11. Maxwell P (2011) Adaptive Testing: Dealing with Process Variability. In Proc. IEEE Design & Test of Computers, vol. 28, no. 6, pp. 41-49

  12. Miyake Y, Kato T, Kajihara S (2020) Path Delay Measurement with Correction for Temperature and Voltage Variations. In Proc.2020 IEEE International Test Conference in Asia (ITC-Asia), pp. 112-117. https://doi.org/10.1109/ITC-Asia51099.2020.00031

  13. Milor L (1998) A tutorial introduction to research on analog and mixed-signal circuit testing. IEEE Trans. Circuits Syst. II: Analog Digital Signal Process., vol. 45, no. 10, pp. 1389-1407

  14. Pomeranz I, Reddy SM (2008) Transition path delay faults: A new path delay fault model for small and large delay defects. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 1, pp. 98-10

  15. Shi CJR, Tian M (1998) Automatic test generation of linear analog circuits under parameter variations. In Proc. IEEE/ACM Des. Automat. Conf., pp. 501-506

  16. Shintani M, Uezono T, Takahashi T, Hatayama K, Aikyo T, Masu K, Sato T (2014) A variability-aware adaptive test flow for test quality improvement. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33(7):1056–1066

    Article  Google Scholar 

  17. Song T, Huang Z, Yan Y (2022) Machine learning classification algorithm for VLSI test cost reduction. Integration. https://doi.org/10.1016/j.mejo.2022.105549

    Article  Google Scholar 

  18. Song T, Liang H, Ni T, Huang Z, Lu Y, Wan J, Yan A (2020) Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm. IEEE Access 8:147965–147972

    Article  Google Scholar 

  19. Song T, Liang H, Sun Y, Huang Z, Yi M, Fang X, Yan A (2019) Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory. VTS 1-6

  20. Stratigopoulos HGD, Drineas P, Slamani M, Makris Y (2007) Non-RF to RF test correlation using learning machines: A case study. In Proc. IEEE VLSI Test Symp., pp. 9-14

  21. Takahashi T, Uezono T, Shintani M, Masu K, Sato T (2009) On-die parameter extraction from path-delay measurements. In Proc. 2009 IEEE Asian Solid-State Circuits Conference, pp. 101-104. https://doi.org/10.1109/ASSCC.2009.5357189

  22. Yilmaz E, Ozev S (2008) Dynamic test scheduling for analog circuits for improved test quality. In Proc IEEE Int Conf Comput Des 227-233

  23. Yilmaz E, Ozev S, Butler K (2010) Adaptive test flow for mixed-signal/RF circuits using learned information from device under test. In Proc IEEE Int Test Conf 1-10

  24. Yuan X, Owczarczyk P, Drake AJ, Tiner MD, Hui DT (2015) Design considerations for reconfigurable delay circuit to emulate system critical paths. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2714-2718

  25. Zhang M, Li H, Li X (2011) Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 11, pp. 1969-1982. https://doi.org/10.1109/TVLSI.2010.2075945

  26. Zolotov V, Xiong J, Fatemi H, Visweswariah C (2010) Statistical path selection for at-speed test. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(5):749–759

    Article  Google Scholar 

Download references

Funding

This work was supported by China Scholarship Council under the CSC No. 202206505003 and in part by the Cooperative Education Project of the Ministry of Education No.220803303162437 and in part by the National Natural Science Foundation of China under the Granted No. 62274052.

Author information

Authors and Affiliations

  1. School of Integrated Circuits, Anhui University, Jiulong 111, Hefei, 230601, Anhui, China

    Tai Song & Xiaohui Guo

  2. School of Microelectronics, Hefei University of Technology, Feicui 420, Hefei, 230009, Anhui, China

    Zhengfeng Huang

  3. System Architectures, IHP - Leibniz-Institut fur innovative Mikroelektronik, Im Technologiepark 25, Frankfurt (Oder), 15236, Brandenburg, Germany

    Krstic Milos

  4. Institute of Computer Science, University of Potsdam, An der Bahn 2, Potsdam, 14476, Brandenburg, Germany

    Krstic Milos

Authors
  1. Tai Song
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Zhengfeng Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Xiaohui Guo
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Krstic Milos
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Tai Song.

Ethics declarations

Conflict of Interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Additional information

Responsible Editor: A. D. Singh

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Song, T., Huang, Z., Guo, X. et al. Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation. J Electron Test 39, 189–205 (2023). https://doi.org/10.1007/s10836-023-06057-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-023-06057-8

Keywords

Search

Navigation