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BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems

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Abstract

The increasing integration of mixed-signal systems in System-on-Chips (SoCs) and System-on-Packages (SoPs) has made pre and post-silicon validation more challenging. This is due to the lack of automated design checking algorithms and the inability to control and observe internal circuit nodes in post-silicon. While digital scan chains can provide observability of internal digital circuit states, analog scan chains encounter issues such as signal integrity, bandwidth, and circuit loading. To address these challenges, a new approach based on built-in state consistency checking (BISCC) is proposed in this paper. The BISCC technique enables both pre and post-silicon validation of mixed-signal/RF systems without the need for manual checks. The approach is supported by a design-for-validation (DfV) methodology, which inserts a minimum amount of circuitry into mixed-signal systems to detect and diagnose design bugs. The core idea is to apply two spectrally diverse stimuli to the circuit under test (CUT) in a way that results in the same circuit state (observed voltage/current values at internal or external circuit nodes). By comparing the resulting state values, design bugs can be detected efficiently without manual checks. The proposed BISCC approach does not make assumptions about the nature of the detected bugs and is steered towards detecting the most likely design bugs. The effectiveness of the approach is demonstrated through test cases for both pre and post-silicon design bug detection and diagnosis.

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Data Availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

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Funding

This research was supported by NSF under Grants CNS 1441754, ECCS 1407542 and by SRC under GRC Task 2555.001.

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Authors and Affiliations

  1. Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta, GA, 30332, USA

    Sabyasachi Deyati, Barry Muldrey & Abhijit Chatterjee

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  1. Sabyasachi Deyati
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  2. Barry Muldrey
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  3. Abhijit Chatterjee
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Correspondence to Sabyasachi Deyati.

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Conflict of Interest

Author Abhijit Chatterjee had received funding for this research from the following sources NSF under Grants CNS 1441754, ECCS 1407542 and by SRC under GRC Task 2555.001. The authors have no relevant financial or non-financial interests to disclose. The authors have no competing interests to declare that are relevant to the content of this article. All authors certify that they have no affiliations with or involvement in any organization or entity with any financial interest or non-financial interest in the subject matter or materials discussed in this manuscript. The authors have no financial or proprietary interests in any material discussed in this article.

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Deyati, S., Muldrey, B. & Chatterjee, A. BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems. J Electron Test 39, 303–322 (2023). https://doi.org/10.1007/s10836-023-06062-x

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