Abstract
SRAM memory systems are suffering from an increase in data due to the aggressive CMOS integration density. The frequency of Multiple Cell Upsets (MCUs) on SRAM memory is increasing, which is resulting in the increasing use of ECCs.Speed is slowed down by ECCs due to their overhead, both in memory bits and decoding times. In this research, Continuous Adjacent Multiple Bit Upset Correction (CAMBUC)has been proposed to greatly reduce the redundancy and improve correction coverage.In addition, the Interleaved Counter Matrix Code (ICMC) is proposed to simplify the Encoder and decoder circuits which reduces the delay. The proposed method predicts MBU before decoding and maximum parallel 8 error bits are corrected using the proposed method. Using this method, the error correction code’s parity check matrix is automatically and effectively constructed, simply stating its error detection and/or correction capabilities. Combinatorial counting operations introduce error detection and error prediction. The proposed ICMC makes use of the decimal and hamming algorithms to achieve the highest level of error detection. In comparison to the conventional decoder, which can rectify double and 8-adjacent errors, the assessment results utilizing the proposed CAMBUC approach demonstrate significant reductions in area, power, and delay. The obtained findings demonstrate that the proposed method has a comparatively long mean time to failure (MTTF) when compared to existing approaches. At the same time, the suggested scheme’s delay overhead is, respectively, 20.5%, 14.6%, 11.2%, 8.5%, and 3.5% less than that of the existing Hamming, CMC, ECC for 5-bit adjacent error, eMRSC, and DICE-7-bit ECCmethods.











Similar content being viewed by others
Data Availability
Data sharing not applicable to this article as no datasets were generated or analyzed during the current study.
References
Maity RK, Tripathi S, Samanta J, Bhaumik J (2020) Lower complexity error location detection block of adjacent error correcting decoder for SRAMs. IET Computers Digit Techniques 14(5):210–216
Ahilan A, Deepa P (2015) A reconfigurable virtual architecture for memory scrubbers (VAMS) for SRAM based FPGA’s. Int J Appl Eng Res 10(10):9643–9648
Argyrides CA, Reviriego P, Pradhan DK, Maestro J (2010) A. Matrix-based codes for adjacent error correction. IEEE Trans Nucl Sci 57(4):2106–2111
Maity RK, Samanta J, Bhaumik J (2023) Single and double-adjacent error correcting code (SDECC) with lower design overheads and mis-correction rate for SRAMs. Microsystem Technologies, pp 1–12
Appathurai A, Deepa P, August (2015) Design for reliablity: A novel counter matrix code for FPGA based quality applications. In 2015 6th Asia Symposium on Quality Electronic Design (ASQED), IEEE, 56–61
Senthil Singh C, Sameena Naaz, Saranya G (2024) Iot-Centric Data Protection using deep learning technique for preserving security and privacy in cloud. Int J Data Sci Artif Intell 02(03):81–87
Sathiya RR, Rajakumar S, Sathiamoorthy J (2023) Secure blockchain based deep learning approach for data transmission in IOT-enabled healthcare system. Int J Comput Eng Optim 01(01):15–23
Maity RK, Samanta J, Bhaumik J (2023) Construction technique and evaluation of high-performance t-bit burst error correcting codes for protecting MCUs. J Circuits Syst Computers 32(09):2350142
Ahilan A, Deepa P, January (2015) Modified Decimal Matrix Codes in FPGA configuration memory for multiple bit upsets. In: 2015 International Conference on Computer Communication and Informatics (ICCCI), IEEE, 1–5
Das A, Touba NA (2019) A new class of single burst error correcting codes with parallel decoding. IEEE Trans Comput 69(2):253–259
Maity RK, Samanta J, Bhaumik J (2022) FPGA-based low delay adjacent triple-bit error correcting codec. In: Internet of Things and its applications: Select Proceedings of ICIA 2020. Springer Nature, Singapore, pp 419–429
Saiz-Adalid LJ, Gracia-MoranJ, Gil-Tomas D, Baraza-CalvoJC, Gil-Vicente PJ (2019) Ultrafast codes for multiple adjacent error correction and double error detection. IEEE Access 7:151131–151143
Prasad SVS, Natarajan PB, Shankar LB, June (2021) Broadening 3-bit burst error-correction codes with quadruple adjacent error correction. In: 2021 International Conference on Intelligent Technologies (CONIT), IEEE, 1–5
AppathuraiAand Deepa P (2016) Radiation induced multiple bit upset prediction and correction in memories using cost efficient CMC. Informacije MIDEM 46(4):257–266
ReviriegoP, Liu S, Xiao L, Maestro JA (2015) An efficient single and double-adjacent error correcting parallel decoder for the (24, 12) extended golay code. IEEE Trans Very Large-Scale Integr (VLSI) Syst 24(4):1603–1606
Li J, Reviriego P, Xiao L, Argyrides C, Li J (2017) Extending 3-bit burst error-correction codes with quadruple adjacent error correction. IEEE Trans Very Large-Scale Integr (VLSI) Syst 26(2):221–229
Gracia-Moran J, Saiz-Adalid LJ, Gil-Tomas D, Gil-Vicente PJ (2018) Improving error correction codes for multiple-cell upsets in space applications. IEEE Trans Very Large-Scale Integr (VLSI) Syst 26(10):2132–2142
Guo J, Xiao L, Mao Z, Zhao Q (2013) Enhanced memory reliability against multiple cell upsets using decimal matrix code. IEEE Trans Very Large-Scale Integr (VLSI) Syst 22(1):127–135
Saiz-Adalid LJ, Reviriego P, Gil P, Pontarelli S, Maestro JA (2014) MCU tolerance in SRAMs through low-redundancy triple adjacent error correction. IEEE Trans Very Large-Scale Integr (VLSI) Syst 23(10):2332–2336
Bhargavi C, Nishanth DV, Nikhita P, Vinodhini M (2014) H-matrix based error correction codes for memory applications. In: 2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), IEEE, 1–5
Argyrides C, Pradhan DK, Kocak T (2019) Matrix codes for reliable and cost-efficient memory chips. IEEE Trans Very Large-Scale Integr (VLSI) Syst 19(3):420–428
Castro HDS, da Silveira JA, Coelho AA, e Silva FG, Magalhães PDS, de Lima OA, June (2016) A correction code for multiple cells upsets in memory devices for space applications. In: 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), IEEE, 1–4
Hamming RW (1950) Error detecting and error correcting codes. Bell Syst Tech J 29(2):147–160
Karan KS, Srikanth N, Agrawal S (2019) A robust code for MBU correction till 5-bit error. In: 2019 International Conference on Communication and Electronics Systems (ICCES). IEEE, pp 1524–1529
Silva F, Freitas W, Silveira J, Marcon C, Vargas F (2020) Extended matrix region selection code: an ECC for adjacent multiple cell upset in memory arrays. Microelectron Reliab 106:113582
Gil-Tomás D, Saiz-Adalid LJ, Gracia-Morán J, Baraza-Calvo JC, Gil-Vicente PJ (2024) A hybrid technique based on ECC and hardened cells for tolerating Random multiple-bit upsets in SRAM arrays. IEEE Access
Ebrahimi M, Rao PMB, Seyyedi R, Tahoori MB (2015) Low-cost multiple bit upset correction in SRAM-based FPGA configuration frames. IEEE Trans Very Large-Scale Integr (VLSI) Syst 24(3):932–943
Acknowledgements
The author would like to acknowledge the Deanship of Graduate Studies and Scientific Research, Taif University for funding this work.
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
Conflict of interest
The authors declare that they have no conflict of interest.
Additional information
Responsible Editor: N. A. Touba
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
About this article
Cite this article
A, A., Gorantla, A., Kiruba, G. et al. Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction. J Electron Test 40, 525–537 (2024). https://doi.org/10.1007/s10836-024-06135-5
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-024-06135-5