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FPGA supported rough set reduct calculation for big datasets

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Abstract

The rough sets theory developed by Prof. Z. Pawlak is one of the tools used in intelligent systems for data analysis and processing. In modern systems, the amount of the collected data is increasing quickly, so the computation speed becomes the critical factor.

One of the solutions to this problem is data reduction. Removing the redundancy in the rough sets can be achieved with the reduct. Most of the algorithms for reduct generation are only software implementations, resulting in many limitations coming from using the fixed word length, as well as consuming the time for fetching and processing of the instructions and data. These limitations make the software-based implementations relatively slow. Unlike software-based systems, hardware systems can process data much faster.

This paper presents FPGA and softcore CPU based device for large datasets reduct calculation using rough set methods. Presented architecture has been tested on two real datasets by downloading and running presented solutions inside FPGA. Tested datasets had 1 000 to 1 000 000 objects. For the research purpose, the algorithm was also implemented in C language and ran on a PC. The time of a reduct calculation in hardware and software was considered. The obtained results show an increase in the speed of data processing.

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Data Availability

In this paper, results were obtained for datasets: Poker Hand Dataset (Cattral et al., 2002) (created by Robert Cattral and Franz Oppacher) and data about children with insulin-dependent diabetes mellitus (type 1) (Stepaniuk, 2000) (created by Jaroslaw Stepaniuk).

Code Availability

The code is protected by the copyright law of the Bialystok Univeristy of Technology.

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Acknowledgements

The work was supported by the grant WZ/WI-IIT/2/2020 from Bialystok University of Technology and funded with resources for research by the Ministry of Science and Higher Education in Poland.

Funding

The work was supported by the grant WZ/WI-IIT/2/2020 from Bialystok University of Technology and funded with resources for research by the Ministry of Science and Higher Education in Poland.

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Authors and Affiliations

  1. Bialystok University of Technology, Wiejska 45A, Bialystok, Poland

    Maciej Kopczynski & Tomasz Grzes

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  1. Maciej Kopczynski
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  2. Tomasz Grzes
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Contributions

All authors contributed to the study conception and design. Material preparation, data collection and analysis were performed by Maciej Kopczynski and Tomasz Grzes. The first draft of the manuscript was written by all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.

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Correspondence to Maciej Kopczynski.

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Kopczynski, M., Grzes, T. FPGA supported rough set reduct calculation for big datasets. J Intell Inf Syst 59, 779–799 (2022). https://doi.org/10.1007/s10844-022-00725-5

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