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Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing

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Abstract

Semiconductor manufacturing processes are very long and complex, needing several hundreds of individual steps to produce the final product (chip). In this context, the early detection of process excursions or product defects is very important to avoid massive potential losses. Metrology is thus a key step in the fabrication line. Whereas a 100 % inspection rate would be ideal in theory, the cost of the metrology devices and cycle time losses due to these measurements would completely inhibit such an approach. On another hand, the skipping of some measurements is risky for quality assurance and processing machine reliability. The purpose is to define an optimized quality control plan that reduces the required capacity of control while maintaining enough trust in quality controls. The method adopted by this research is to employ a multi-objective genetic algorithm to define the optimized control plan able to reduce the used metrology capacity without increasing risk level. Early results based on one month of real historical data computation reveal a possible reallocation of controls with a decrease by more than 15 % of metrology capacity while also reducing the risk level on the processing machine (expressed by the wafer at risk (\(W\!@\!R\))) by 30 %.

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Acknowledgments

This article describes the research conducted within the context of the IMPROVE and INTEGRATE Projects. It has been finalized with the support of dis544 covery Grants founded by NSERC, under the number RGPIN418674-12 CRSNG NIP392730. The authors warmly thank STMicroelectronics for providing data and support for their research. Special thanks to the industrial and process control team for their daily involvement and support in helping us achieve sound results in the projects. Authors thank also the Rhone Alpes Region.

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Authors and Affiliations

  1. IRISE/CESI, 76130, Mont St Aignan, France

    M’hammed Sahnoun

  2. Department of Mathematics and Industrial Engineering, Polytechnique Montréal, Montreal, Canada

    Belgacem Bettayeb & Samuel-Jean Bassetto

  3. University of Grenoble Alpes, G-SCOP, 38000 , Grenoble, France

    Michel Tollenaere

  4. CNRS, G-SCOP, 38000 , Grenoble, France

    Michel Tollenaere

Authors
  1. M’hammed Sahnoun
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  2. Belgacem Bettayeb
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  3. Samuel-Jean Bassetto
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  4. Michel Tollenaere
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Correspondence to Belgacem Bettayeb.

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Sahnoun, M., Bettayeb, B., Bassetto, SJ. et al. Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing. J Intell Manuf 27, 1335–1349 (2016). https://doi.org/10.1007/s10845-014-0956-x

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  • DOI: https://doi.org/10.1007/s10845-014-0956-x

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