Abstract
This work presents an online decentralized allocation algorithm of a safety-critical application on parallel computing architectures, where individual Computational Units can be affected by faults. The described method includes representing the architecture by an abstract graph where each node represents a Computational Unit. Applications are also represented by the graph of Computational Units they require for execution. The problem is then to decide how to allocate Computational Units to applications to guarantee execution of a safety-critical application. The problem is formulated as an optimization problem with the form of an Integer Linear Program. A state-of-the-art solver is then used to solve the problem. Decentralizing the allocation process is achieved through redundancy of the allocator executed on the architecture. No centralized element decides on the allocation of the entire architecture, thus improving the reliability of the system. Inspired by multi-core architectures in avionics systems, an experimental illustration of the work is also presented. It is used to demonstrate the capabilities of the proposed allocation process to maintain the operation of a physical system in a decentralized way while individual components fail.
Similar content being viewed by others
Notes
This does not mean that this communication link cannot be used for other communication purposes on the architecture, but only one of the Application Links computed by the compiler for the applications can be allocated to that physical communication link.
References
Al Sheikh, A., Brun, O., Hladik, P.E., Prabhu, B.J.: Strictly periodic scheduling in IMA-based architectures. Real-Time Syst. 48(4), 359–386 (2012)
Alle, M., Varadarajan, K., Fell, A., Reddy, C.R., Nimmy, J., Das, S., Biswas, P., Chetia, J., Rao, A., Nandy, S.K., Narayan, R.: REDEFINE: runtime reconfigurable polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9(2), 1008–1014 (2009)
Avakian, A., Nafziger, J., Panda, A., Vemuri, R.: A reconfigurable architecture for multicore systems. In: 2010 IEEE International Symposium on Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW), pp. 1–8 (2010). https://doi.org/10.1109/IPDPSW.2010.5470753
Ben Cheikh, T.L., Beltrame, G., Nicolescu, G., Cheriet, F., Tahar, S.: Parallelization strategies of the canny edge detector for multi-core CPUs and many-core GPUs. In: 10th IEEE International NEWCAS Conference, pp. 49–52 (2012). https://doi.org/10.1109/NEWCAS.2012.6328953
Berthe, B.: A380 ATA 42 certification. CISEC IMA day, Toulouse (2007)
Chen, T.P., Budnikov, D., Hughes, C.J., Chen, Y.: Computer vision on multi-core processors: Articulated body tracking. In: 2007 IEEE International Conference on Multimedia and Expo, pp. 1862–1865 (2007). https://doi.org/10.1109/ICME.2007.4285037
Durak, U., Bapp, F.: Introduction to special issue on multi-core architectures in avionics systems. J. Aerospace Inf. Syst. 16(11), 441 (2019). https://doi.org/10.2514/1.I010793
Everitt, T., Hutter, M.: Analytical results on the BFS vs. DFS algorithm selection problem: Part II: Graph search. In: Australasian Joint Conference on Artificial Intelligence, pp. 166–178. Springer, Berlin (2015)
Hackenberg, D.L.: NASA aeronautics research mission directorate (ARMD) urban air mobility (UAM) grand challenge industry day. NASA Technical Reports (2018). https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20190003422
Hang, C., Manolios, P., Papavasileiou, V.: Synthesizing cyber-physical architectural models with real-time constraints. In: International Conference on Computer Aided Verification, pp. 441–456. Springer, Berlin (2011)
Hasan, S.: Urban air mobility (UAM) market study. NASA Technical Reports (2019). https://ntrs.nasa.gov/search.jsp?R=20190026762
Hillier, F.S., Lieberman, G.J.: Introduction to Operations Research, 10th edn. McGraw-Hill, New York (2015)
Israel Koren, C.M.K.: Fault Tolerant Systems. Morgan Kaufmann Publishers, Burlington (2007)
Johnson, W., Silva, C., Solis, E.: Concept vehicles for VTOL air taxi operations. NASA Technical Reports (2018). https://ntrs.nasa.gov/search.jsp?R=20180003381
Khamvilai, T.: Decentralized control of electrical duct fan (2020). https://doi.org/10.6084/m9.figshare.13336796.v1. https://figshare.com/articles/media/Decentralized_Control_of_Electrical_Duct_Fan/13336796
Khamvilai, T., Sutter, L., Mains, J.B., Feron, E., Baufreton, P., Neumann, F., Krishna, M., Nandy, S.K., Narayan, R., Haldar, C.: Task allocation of safety-critical applications on reconfigurable multi-core architectures with an application on control of propulsion system. In: 2019 IEEE/AIAA 38th Digital Avionics Systems Conference (DASC) (2019)
Kinnan, L.M.: Use of multicore processors in avionics systems and its potential impact on implementation and certification. In: Digital Avionics Systems Conference, 2009. DASC’09. IEEE/AIAA 28th, pp. 1–E. IEEE (2009)
Köppe, M.: On the complexity of nonlinear mixed-integer optimization. In: Mixed Integer Nonlinear Programming, pp. 533–557. Springer, Berlin (2012)
Li, J., Ming, Z., Qiu, M., Quan, G., Qin, X., Chen, T.: Resource allocation robustness in multi-core embedded systems with inaccurate information. J. Syst. Architect. 57(9), 840–849 (2011)
Loekstad, T., Reichenbach, F.: Symmetric multi-processor arrangement, safety critical system, and method therefor (2015). US Patent App. 14/432,938
Löfwenmark, A., Nadjm-Tehrani, S.: Challenges in future avionic systems on multi-core platforms. In: 2014 IEEE International Symposium on Software Reliability Engineering Workshops, pp. 115–119. IEEE (2014)
Lu, Y., Zhou, H., Shang, L., Zeng, X.: Multicore parallelization of min-cost flow for CAD applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10), 1546–1557 (2010). https://doi.org/10.1109/TCAD.2010.2061150
Mains, J.B.: Scheduling and assignment on dynamic processor networks (Master Thesis). Georgia Institute of Technology (2020)
Makhorin, A.: GLPK (GNU linear programming kit). http://www.gnu.org/s/glpk/glpk.html (2008)
Manolios, P., Papavasileiou, V.: ILP modulo theories. In: International Conference on Computer Aided Verification, pp. 662–677. Springer, Berlin (2013)
Manolios, P., Vroon, D., Subramanian, G.: Automating component-based system assembly. In: Proceedings of the 2007 International Symposium on Software Testing and Analysis, pp. 61–72 (2007)
Mesbahi, M., Egerstedt, M.: Graph Theoretic Methods in Multiagent Networks, vol. 33. Princeton University Press, Princeton (2010)
Moir, I., Seabridge, A., Jukes, M.: Civil Avionics Systems. Wiley, New York (2013)
Monot, A., Navet, N., Bavoux, B., Simonot-Lion, F.: Multisource software on multicore automotive ECUs–combining runnable sequencing with task scheduling. IEEE Trans. Ind. Electron. 59(10), 3934–3942 (2012). https://doi.org/10.1109/TIE.2012.2185913
Neves, N., Sebastião, N., Matos, D., Tomás, P., Flores, P., Roma, N.: Multicore SIMD ASIP for next-generation sequencing and alignment biochip platforms. IEEE Trans. Very Large Scale Integr. VLSI Syst. 23(7), 1287–1300 (2015). https://doi.org/10.1109/TVLSI.2014.2333757
Nowotsch, J., Paulitsch, M.: Leveraging multi-core computing architectures in avionics. In: Dependable Computing Conference (EDCC), 2012 Ninth European, pp. 132–143. IEEE (2012)
Oriol, M., Gamer, T., de Gooijer, T., Wahler, M., Ferranti, E.: Fault-tolerant fault tolerance for component-based automation systems. In: Proceedings of the 4th international ACM Sigsoft symposium on Architecting critical systems, pp. 49–58 (2013). https://doi.org/10.1145/2465470.2465471
Parkinson, P.J.: The Challenges of Developing Embedded Real-Time Aerospace Applications on Next Generation Multi-core Processors. Aviation Electronics Europe, Munich (2016)
Reichenbach, F., Wold, A.: Multi-core technology–next evolution step in safety critical systems for industrial applications? In: Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on, pp. 339–346. IEEE (2010)
SAE: Guidelines and methods for conducting the safety assessment process on civil airborne systems and equipment. London-UK: SAE ARP4761 (1996)
Shen, Y., Wu, J., Jiang, G.: Multithread reconfiguration algorithm for mesh-connected processor arrays. In: 2012 13th International Conference on Parallel and Distributed Computing, Applications and Technologies, pp. 659–663 (2012). https://doi.org/10.1109/PDCAT.2012.99
Silva, C., Johnson, W.R., Solis, E., Patterson, M.D., Antcliff, K.R.: VTOL urban air mobility concept vehicles for technology development. In: 2018 Aviation Technology, Integration, and Operations Conference, p. 3847 (2018)
Stuart, M.B., Stensgaard, M.B., Sparsø, J.: The ReNoC reconfigurable network-on-chip: architecture, configuration algorithms, and evaluation. ACM Trans. Embedded Comput. Syst. (TECS) 10(4), 1–26 (2011)
Sutter, L., Khamvilai, T., Monmousseau, P., Mains, J.B., Feron, E., Baufreton, P., Neumann, F., Krishna, M., Nandy, S.K., Narayan, R., Haldar, C.: Experimental allocation of safety-critical applications on reconfigurable multi-core architecture. In: 2018 IEEE/AIAA 37th Digital Avionics Systems Conference (DASC), pp. 1–10 (2018). https://doi.org/10.1109/DASC.2018.8569348
Upton, E., Halfacree, G.: Raspberry PI User Guide. Wiley, New York (2014)
Watkins, M.A., Albonesi, D.H.: ReMAP: A reconfigurable heterogeneous multicore architecture. In: 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 497–508 (2010). https://doi.org/10.1109/MICRO.2010.15
Zhong, Z., Edahiro, M.: Model-based parallelization for simulink models on multicore CPUs and GPUs. Int. J. Comput. Technol. 20, 1–13 (2020). https://doi.org/10.24297/ijct.v20i.8533
Acknowledgements
This effort has been funded in part by SAFRAN, by the KAUST baseline fund, and by the National Science Foundation, Grants CNS 1544332 and 1446758. We would like to thank Philippe Monmousseau for his work on prioritizing the applications.
Author information
Authors and Affiliations
Corresponding author
Additional information
Communicated by Mauro Pontani.
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Eric Feron: On Leave from Georgia Institute of Technology.
Appendix A
Appendix A
This appendix provides the proof that the coefficients in the objective function from Eq. (3) allow to meet all three requirements stated in Sect. 3.3.
Theorem A.1
that is, the contribution to the value of the objective function for executing application \(\mathrm {app}_{{\tilde{k}}}\) is greater than the maximum contribution for reducing the number of reallocations and the length of the communication paths.
Proof
\(\forall \ {\tilde{k}} \in \llbracket 1,\ N_{\mathrm{apps}} \rrbracket : \alpha _{{\tilde{k}}} \ge (\beta +1) \times N_{\mathrm{nodes}} + \beta ,\) by definition of \(\alpha _{{\tilde{k}}}\).
Now,
So
\(\square \)
Theorem A.1 proves that requirement 1 is met.
Theorem A.2
that is, the contribution to the value of the objective function for not reallocating one Application node is greater then the maximum contribution for reducing the length of communication paths.
Proof
\( \beta + 1 > \beta = N_{\mathrm{realloc}} \times N_{\mathrm{CUs}} \times N_{\mathrm{paths}} = \sum _{k = 1}^{N_{\mathrm{realloc}}}\sum _{j = 1}^{N_{\mathrm{CUs}}}\sum _{i = 1}^{N_{\mathrm{paths}}} 1 \). \(\square \)
Theorem A.2 proves that requirement 2 is met.
Theorem A.3
that is, the contribution to the value of the objective function for executing application \(\mathrm {app}_{{\tilde{k}}}\) is greater than the contribution for executing every applications with lower priority than \(\mathrm {app}_{{\tilde{k}}}\), which are \(\mathrm {app}_{{\tilde{k}}+1}\) to \(\mathrm {app}_{N_{\mathrm{apps}}}\).
Proof
\(\forall \ {\tilde{k}} \in \llbracket 1,\ N_{\mathrm{apps}} \rrbracket :\alpha _{{\tilde{k}}} = \sum _{l = {\tilde{k}}+1}^{N_{\mathrm{apps}}} \alpha _l + (\beta +1) \times N_{\mathrm{nodes}} + \beta + 1 > \sum _{l = {\tilde{k}}+1}^{N_{\mathrm{apps}}} \alpha _l \)
since \( (\beta +1) \times N_{\mathrm{nodes}} + \beta + 1 > 0 \). \(\square \)
Theorem A.3 proves that requirement 3 is met.
Rights and permissions
About this article
Cite this article
Khamvilai, T., Sutter, L., Baufreton, P. et al. Decentralized Task Reallocation on Parallel Computing Architectures Targeting an Avionics Application. J Optim Theory Appl 191, 874–898 (2021). https://doi.org/10.1007/s10957-021-01862-7
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10957-021-01862-7
Keywords
- Parallel computing
- Distributed computing
- Reconfigurable
- Safety-critical
- Fault tolerance
- Avionics
- Integer linear programming