A video decoding optimization for heterogeneous dual-core platforms architecture

Abstract

Digital signal processors (DSPs), with their powerful computing abilities, are commonly used for multimedia coding/decoding processes. Therefore, the SOC (System on Chip) industry integrates DSP with ARM (Advanced RISC Machine) for input/output processing, saving power, and building up a multi-core platform used in handheld devices. The computing ability of ARM has been substantially improved with some state of the art technique. The industry currently has regarded the integration of ARM and DSP into SOC as two independent cores to enhance the efficiency. Since one algorithm is added to process the distributed computing work of the dual cores, the efficiency must be doubled. The system will assign the work to the core with higher processing efficiency. Instead of the traditional Static task scheduling, this article proposed a new approach called Dynamic task scheduling, providing 29.88 % higher efficiency than that of Static task scheduling. The reason is that the static partition will finally send the heavy load of computing to DSP; therefore, it is not possible to achieve the enhanced efficiency of the multi-core. However, the dynamic task scheduling will consider the actual loading of each core for computing and communicate with each other; furthermore, it can share the work to assist the process of each core. Besides, the Direct Memory Access is integrated with the multi-core platform to reduce the time-consumption resulted from the communication between the dual cores. The experimental result shows that the dynamic partition operated by the heterogeneous dual core system can use 192 MHz pulse to decode the CIF video signal that the decoding speed can reach 30fps and the efficiency is improved 50 % with DMA (Direct Memory Access) technology incorporated.