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Parallel design and implementation of Error Diffusion Algorithm and IP core for FPGA

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Abstract

This paper offers an improved error diffusion algorithm for its real-time implementation in FPGA by creating Error-Error Diffusion Value Lookup Tables to spare multiplications, adopting four pipelines instead of traditional sequential process, and performing color error diffusion in four parallel channels among other techniques whereby it takes only one clock circle on average to get the halftone result of a pixel. In accordance with the Avalon bus specification, the improved algorithm is packaged into an IP core which is later adopted to construct a practical halftoning hardware system using the SOPC technique. Tests of the system in the “USB Direct Printing System” of the research office show that the IP core is efficient to meet the requirements of the printing domain.

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Authors and Affiliations

  1. School of Computer Science and Technology, Xidian University, Xi’an, China

    Pengfei Yang, Quan Wang & Jiyang Zhang

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  1. Pengfei Yang
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  2. Quan Wang
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  3. Jiyang Zhang
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Correspondence to Pengfei Yang.

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Yang, P., Wang, Q. & Zhang, J. Parallel design and implementation of Error Diffusion Algorithm and IP core for FPGA. Multimed Tools Appl 75, 4723–4733 (2016). https://doi.org/10.1007/s11042-015-2499-3

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  • DOI: https://doi.org/10.1007/s11042-015-2499-3

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