Skip to main content
Log in

Prediction complexity-based HEVC parallel processing for asymmetric multicores

  • Published:
Multimedia Tools and Applications Aims and scope Submit manuscript

Abstract

This paper proposes a novel Tile allocation method considering the computational ability of asymmetric multicores as well as the computational complexity of each Tile. This paper measures the computational ability of asymmetric multicores in advance, and measures the computational complexity of each Tile by using the amount of HEVC prediction unit (PU) partitioning. The implemented system counts and sorts the amount of PU partitions of each Tile, and also allocates Tiles to asymmetric big.LITTLE cores according to their expected computational complexity. When experiments were conducted, the amount of PU partitioning and the computational complexity (decoding time) showed a close correlation, and average performance gains of decoding time with the proposed adaptive allocation were around 36 % with 12 Tiles, 28 % with 18 Tiles, and 31 % with 24 Tiles, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. Ahn H, Jeong S (2013) Power-minimizing dvfs algorithm using estimation of video frame decoding complexity. J Kor Inst Commun Inf Sci 38(1):46–53

    Google Scholar 

  2. Baik H, Song H (2015) A complexity-based adaptive tile partitioning algorithm for HEVC decoder parallelization. In: 2015 IEEE international conference on image processing (ICIP). IEEE, pp 4298– 4302

  3. Blem E, Menon J, Sankaralingam K (2013) Power struggles: Revisiting the risc vs. cisc debate on contemporary arm and x86 architectures. In: 2013 IEEE 19th international symposium on high performance computer architecture (HPCA2013). IEEE, pp 1–12

  4. Bossen F, Bross B, Suhring K, Flynn D (2012) HEVC complexity and implementation analysis. IEEE Trans Circuits Syst Video Technol 22(12):1685–1696

    Article  Google Scholar 

  5. Carroll A, Heiser G (2014) Unifying dvfs and offlining in mobile multicores. In: 2014 IEEE 19th real-time and embedded technology and applications symposium (RTAS). IEEE, pp 287–296

  6. Koufaty D, Reddy D, Hahn S (2010) Bias scheduling in heterogeneous multi-core architectures. In: Proceedings of the 5th European conference on Computer systems. ACM, pp 125–138

  7. Misra K, Segall A, Horowitz M, Xu S, Fuldseth A, Zhou M (2013) An overview of tiles in HEVC. IEEE J Sel Top Sign Proces 7(6):969–977

    Article  Google Scholar 

  8. Ohm JR, Sullivan GJ, Schwarz H, Tan TK, Wiegand T (2012) Comparison of the coding efficiency of video coding standards–including high efficiency video coding (HEVC). IEEE Trans Circuits Syst Video Technol 22(12):1669–1684

    Article  Google Scholar 

  9. Pricopi M, Muthukaruppan TS, Venkataramani V, Mitra T, Vishin S (2013) Power-performance modeling on asymmetric multi-cores. In: 2013 international conference on compilers, architecture and synthesis for embedded systems (CASES). IEEE, pp 1–10

  10. Shelepov D, Saez Alcaide JC, Jeffery S, Fedorova A, Perez N, Huang ZF, Blagodurov S, Kumar V (2009) Hass: a scheduler for heterogeneous multicore systems. ACM SIGOPS Operating Syst Rev 43(2):66– 75

    Article  Google Scholar 

  11. Springer D, Schnurrer W, Weinlich A, Heindel A, Seiler J, Kaup A (2014) Open source HEVC analyzer for rapid prototyping (harp). In: 2014 IEEE international conference on image processing (ICIP). IEEE, pp 2189–2191

  12. Sullivan GJ, Ohm JR, Han WJ, Wiegand T (2012) Overview of the high efficiency video coding (HEVC) standard. IEEE Trans Circuits Syst Video Technol 22(12):1649–1668

    Article  Google Scholar 

  13. Sullivan GJ, Topiwala PN, Luthra A (2004) The H. 264/AVC advanced video coding standard: Overview and introduction to the fidelity range extensions. In: Optical Science and Technology, the SPIE 49th Annual Meeting. International Society for Optics and Photonics, pp 454–474

  14. Yoo S, Shim Y, Lee S, Lee SA, Kim J (2015) A case for bad big. little switching: How to scale power-performance in si-hmp. In: Proceedings of the workshop on power-aware computing and systems. ACM, pp 1–5

Download references

Acknowledgments

This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Science, ICT & Future Planning (NRF-2015R1C1A1A02037743).

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Eun-Seok Ryu.

Additional information

Hyun-Joon Roh and Sung Won Han contributed equally to this work.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Roh, HJ., Han, S.W. & Ryu, ES. Prediction complexity-based HEVC parallel processing for asymmetric multicores. Multimed Tools Appl 76, 25271–25284 (2017). https://doi.org/10.1007/s11042-017-4413-7

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11042-017-4413-7

Keywords