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Energy efficient processing of motion estimation for embedded multimedia systems

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Abstract

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions.

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Acknowledgements

This work was supported by 2016 Hongik University Research Fund. Additionally, the author would like to acknowledge Xilinx and the Xilinx University Program for its generous donation of S/W design tools and H/W boards.

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  1. Hongik University, Sejong, Republic of Korea

    Jooheung Lee

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  1. Jooheung Lee
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Correspondence to Jooheung Lee.

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Lee, J. Energy efficient processing of motion estimation for embedded multimedia systems. Multimed Tools Appl 76, 24749–24765 (2017). https://doi.org/10.1007/s11042-017-4645-6

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  • DOI: https://doi.org/10.1007/s11042-017-4645-6

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