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Hardware-software implementation of HEVC decoder on Zynq

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Abstract

This paper presents an efficient implementation of the High Efficiency Video Coding (HEVC) decoder using Hardware/Software (HW/SW) co-design approach on the Zynq System on Chip (SoC) Platform. The reference software decoder HM 10.0 has been implemented under embedded Linux Operating System (OS). For real-time decoding, we provide hardware acceleration for the most computationally intensive parts of the HEVC decoder, which are the interpolation filters. The proposed design improves the processing throughput targeting on the resolution of 3840 × 2160 at a frame rate of 60 fps. HW/SW validation is achieved and examined in terms of resource utilization, throughput and power consumption. In order to improve the total decoding time, we propose to enable the Direct Memory Access (DMA) mode that can help speed page access and minimize the transfer time between the processor and hardware accelerators.

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Authors and Affiliations

  1. National School of Engineering, Electronics and Information Technology Laboratory, University of Sfax, 3038, Sfax, Tunisia

    Lella Aicha Ayadi, Hassen Loukil & Nouri Masmoudi

  2. National School of Electronics and Telecommunications, New Technologies and Telecommunication Systems Research Unit, University of Sfax, 3018, Sfax, Tunisia

    Mohamed Ali Ben Ayed

Authors
  1. Lella Aicha Ayadi
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  2. Hassen Loukil
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  3. Mohamed Ali Ben Ayed
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  4. Nouri Masmoudi
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Correspondence to Lella Aicha Ayadi.

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Ayadi, L.A., Loukil, H., Ayed, M.A.B. et al. Hardware-software implementation of HEVC decoder on Zynq. Multimed Tools Appl 79, 7685–7703 (2020). https://doi.org/10.1007/s11042-019-08548-3

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  • DOI: https://doi.org/10.1007/s11042-019-08548-3

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