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Performance-driven parallel reconfigurable computing architecture for multi-standard video decoding

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Abstract

Video processing applications often need high computing capacity but have performance and power constraints, especially in portable devices. General purpose processors can no longer meet the requirements. This paper presents a parallel reconfigurable computing architecture consisting of reconfigurable processing units connected by an area-efficient routing. The hierarchical configuration contexts can cut the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed architecture targets multiple-standard video processing. The design is able to give high performance comparable to the fixed-function ASIC through deep pipelining and a large amount of computing parallelism. The experimental results show the proposed architecture has great performance and practicability.

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Funding

This work was supported by Ministry of Science and Technology, Taiwan, MOST 106–2221-E-024-005 and National University of Tainan, Taiwan, AB108–207.

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  1. Department of Computer Science and Information Engineering, National University of Tainan, Tainan, Taiwan

    Chi-Chou Kao

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  1. Chi-Chou Kao
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Correspondence to Chi-Chou Kao.

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Kao, CC. Performance-driven parallel reconfigurable computing architecture for multi-standard video decoding. Multimed Tools Appl 79, 30583–30599 (2020). https://doi.org/10.1007/s11042-020-09505-1

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