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Reduction of drain induced barrier lowering by optimization Trimetal- GAA -Si -NW MOSFET in multimedia tools

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Abstract

To keep continue the miniaturization of VLSI technology a Trimetal asymmetrical gate all around (TG-GAA) device is proposed to narrow the short channel effects of the scaling down of devices in terms of the improved subthreshold slope by reducing the leakage current up to 2.37E−13 A and have the better control on the channel at lower supply voltages from 0.1 V to 1 V. The analytical electrical field distribution, channel length characterization and potential profile of the proposed device based on Gate all around Silicon nanowire MOSFET channel are enclosed by the Trimetal gate have been observed Using 2-D Poisson equation by considering parabolic approximation with appropriate boundary condition in cylindrical coordinates. Further subthreshold drain current model is derived by applying derived potential profile at subthreshold condition by considering the diffusion transportation. The surface & centre potential has been carried out to satisfy the basic optimum parameters for this new structure, which further supports that the DIBL effects was been minimized and observed that by reducing silicon thickness at (tSi =5 nm) lower leakage current 2.37E-13A and improved drain current(Id) of 2.159E-05A is obtained. Further proposed device exhibit decline DIBL of 23.3 mV/V, magnificent subthreshold slope 63.5 mV/decade and improved higher threshold voltage improved ON/OFF ratio. Additionally, well agreement has been observed between the derived 2-D analytical model with the simulated results obtained from numerical simulator Cogenda visual TCAD.

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Authors and Affiliations

  1. Department of ECE, SOEEC. ADAMA University of Science & Technology, Adama, Ethiopia

    Davinder Singh Rathee

  2. EE Department, UIET, MDU, Rohtak, India

    Davinder Singh Rathee

  3. ECE Department, Punjab Technical University, Jalandhar, India

    Ritu Yadav

  4. ECE Departments, DAV College, Jalandhar, India

    Kiran Ahuja

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  1. Davinder Singh Rathee
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  2. Ritu Yadav
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  3. Kiran Ahuja
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Correspondence to Davinder Singh Rathee.

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Rathee, D.S., Yadav, R. & Ahuja, K. Reduction of drain induced barrier lowering by optimization Trimetal- GAA -Si -NW MOSFET in multimedia tools. Multimed Tools Appl 81, 19849–19862 (2022). https://doi.org/10.1007/s11042-021-11518-3

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  • DOI: https://doi.org/10.1007/s11042-021-11518-3

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