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FPGA implementation of EFSME for high efficient video coding standard

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Abstract

Nowadays, High Efficiency Video Coding (HEVC) is widely used in video compression techniques due to the utilization of less bit rate than Advanced Video Coding (AVC) encoders. Motion Estimation (ME) is a vital task in HEVC video compression technique which consumes more encoding time. Various algorithms are proposed in existing studies to deal with ME process in HEVC. Full Search Motion Estimation (FSME) method is most suitable for HEVC because, it is better in terms of high data flow and operating speed. In this work, Particle Swarm Optimization (PSO) is proposed to optimize Sum of Absolute Difference (SAD) calculation value hence, it is named as Enhanced FSME (EFSME). SAD calculation of EFSME not requires adder tree, comparison block and control unit. Hence, there is great reduction in area, power and operating frequency. Proposed work is implemented in Xilinx ZYNQ XA7Z010 FPGA board and it is evaluated by means of power, area and operational frequency. For HEVC, EFSME outputs 65 mW as power consumption rate which is 28.94% lower than Vayalil et al. (2017), 3.03% lesser than Xu et al. (2018) and 80.05% lesser than Singh and Ahamed (2018). Moreover, the proposed design accomplishes 431.906 MHz as operating speed that is 0.44% greater than Vayalil et al. (2017), 20.95% higher than Xu et al. (2018) and 53.35% higher than Singh and Ahamed (2018). Overall, the simulation results proved that the proposed enhanced architecture is better than the existing methodologies in terms of different parameters.

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  1. Department of EEE, BITS Pilani, Hyderabad Campus, Hyderabad, 500078, India

    Sumit Kumar Chatterjee & Sravan Kumar Vittapu

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  1. Sumit Kumar Chatterjee
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  2. Sravan Kumar Vittapu
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Correspondence to Sumit Kumar Chatterjee.

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Chatterjee, S.K., Vittapu, S.K. FPGA implementation of EFSME for high efficient video coding standard. Multimed Tools Appl 81, 34087–34103 (2022). https://doi.org/10.1007/s11042-022-13051-3

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  • DOI: https://doi.org/10.1007/s11042-022-13051-3

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