Abstract
The design of Digital Signal Processing systems involving video data has many challenges other than the optimal design of the processing algorithms. The data handling starting from the raw data storage and retrieval for efficient processing to store back for further analysis, has many challenges. The memory data layout, access patterns, and interface design are critical factors that need more investigation in the architectural design of video processing systems in general. With the increase in video post-processing algorithms’ complexity, the memory access pattern is turning more and more irregular. Unless the memory data layout, i.e., data storage pattern across the Dynamic Random Access Memory (DRAM), is tailored to the application, the memory bandwidth and power dissipation will be affected adversely. Memory efficiency in terms of throughput and energy consumption plays a vital role in deciding the overall efficiency of such systems involving a massive volume of data. An exhaustive analysis of different memory data layouts and access patterns for video data received in raster scan order and processed in blocks is conducted in this work. A Field Programmable Gate Array (FPGA) based video stabilization system for marine surveillance using inbuilt memory controller Intellectual Property (IP) is the user application under consideration. The optimal memory data layout and access patterns for this system are proposed here, and we can extend the findings from this study to many other application scenarios.
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Unnikrishnan, S., G, S. Performance analysis of memory data layout for sub-block data access. Multimed Tools Appl 82, 7229–7245 (2023). https://doi.org/10.1007/s11042-022-13564-x
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DOI: https://doi.org/10.1007/s11042-022-13564-x